diff options
Diffstat (limited to 'arch/blackfin/mach-common')
| -rw-r--r-- | arch/blackfin/mach-common/clocks-init.c | 3 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/entry.S | 9 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/head.S | 84 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/interrupt.S | 2 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 11 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/pm.c | 11 |
6 files changed, 54 insertions, 66 deletions
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index 5d182abefc7b..9dddb6f8cc85 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <asm/clocks.h> | 14 | #include <asm/clocks.h> |
| 15 | #include <asm/mem_init.h> | 15 | #include <asm/mem_init.h> |
| 16 | 16 | ||
| 17 | #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ | ||
| 17 | #define PLL_CTL_VAL \ | 18 | #define PLL_CTL_VAL \ |
| 18 | (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ | 19 | (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ |
| 19 | (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) | 20 | (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) |
| @@ -76,7 +77,7 @@ void init_clocks(void) | |||
| 76 | bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | 77 | bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); |
| 77 | #ifdef EBIU_SDGCTL | 78 | #ifdef EBIU_SDGCTL |
| 78 | bfin_write_EBIU_SDRRC(mem_SDRRC); | 79 | bfin_write_EBIU_SDRRC(mem_SDRRC); |
| 79 | bfin_write_EBIU_SDGCTL(mem_SDGCTL); | 80 | bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); |
| 80 | #else | 81 | #else |
| 81 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); | 82 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); |
| 82 | do_sync(); | 83 | do_sync(); |
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index fae774651374..88de053bbe8e 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S | |||
| @@ -151,13 +151,6 @@ ENTRY(_ex_syscall) | |||
| 151 | jump.s _bfin_return_from_exception; | 151 | jump.s _bfin_return_from_exception; |
| 152 | ENDPROC(_ex_syscall) | 152 | ENDPROC(_ex_syscall) |
| 153 | 153 | ||
| 154 | ENTRY(_ex_soft_bp) | ||
| 155 | r7 = retx; | ||
| 156 | r7 += -2; | ||
| 157 | retx = r7; | ||
| 158 | jump.s _ex_trap_c; | ||
| 159 | ENDPROC(_ex_soft_bp) | ||
| 160 | |||
| 161 | ENTRY(_ex_single_step) | 154 | ENTRY(_ex_single_step) |
| 162 | /* If we just returned from an interrupt, the single step event is | 155 | /* If we just returned from an interrupt, the single step event is |
| 163 | for the RTI instruction. */ | 156 | for the RTI instruction. */ |
| @@ -1087,7 +1080,7 @@ ENTRY(_ex_table) | |||
| 1087 | * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined | 1080 | * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined |
| 1088 | */ | 1081 | */ |
| 1089 | .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */ | 1082 | .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */ |
| 1090 | .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */ | 1083 | .long _ex_trap_c /* 0x01 - User Defined - Software breakpoint */ |
| 1091 | #ifdef CONFIG_KGDB | 1084 | #ifdef CONFIG_KGDB |
| 1092 | .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection | 1085 | .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection |
| 1093 | and break signal trap */ | 1086 | and break signal trap */ |
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S index e1e42c029e15..698d4c05947e 100644 --- a/arch/blackfin/mach-common/head.S +++ b/arch/blackfin/mach-common/head.S | |||
| @@ -17,6 +17,19 @@ | |||
| 17 | 17 | ||
| 18 | __INIT | 18 | __INIT |
| 19 | 19 | ||
| 20 | ENTRY(__init_clear_bss) | ||
| 21 | r2 = r2 - r1; | ||
| 22 | cc = r2 == 0; | ||
| 23 | if cc jump .L_bss_done; | ||
| 24 | r2 >>= 2; | ||
| 25 | p1 = r1; | ||
| 26 | p2 = r2; | ||
| 27 | lsetup (1f, 1f) lc0 = p2; | ||
| 28 | 1: [p1++] = r0; | ||
| 29 | .L_bss_done: | ||
| 30 | rts; | ||
| 31 | ENDPROC(__init_clear_bss) | ||
| 32 | |||
| 20 | #define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) | 33 | #define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) |
| 21 | 34 | ||
| 22 | ENTRY(__start) | 35 | ENTRY(__start) |
| @@ -144,6 +157,35 @@ ENTRY(__start) | |||
| 144 | call _init_early_exception_vectors; | 157 | call _init_early_exception_vectors; |
| 145 | #endif | 158 | #endif |
| 146 | 159 | ||
| 160 | r0 = 0 (x); | ||
| 161 | /* Zero out all of the fun bss regions */ | ||
| 162 | #if L1_DATA_A_LENGTH > 0 | ||
| 163 | r1.l = __sbss_l1; | ||
| 164 | r1.h = __sbss_l1; | ||
| 165 | r2.l = __ebss_l1; | ||
| 166 | r2.h = __ebss_l1; | ||
| 167 | call __init_clear_bss | ||
| 168 | #endif | ||
| 169 | #if L1_DATA_B_LENGTH > 0 | ||
| 170 | r1.l = __sbss_b_l1; | ||
| 171 | r1.h = __sbss_b_l1; | ||
| 172 | r2.l = __ebss_b_l1; | ||
| 173 | r2.h = __ebss_b_l1; | ||
| 174 | call __init_clear_bss | ||
| 175 | #endif | ||
| 176 | #if L2_LENGTH > 0 | ||
| 177 | r1.l = __sbss_l2; | ||
| 178 | r1.h = __sbss_l2; | ||
| 179 | r2.l = __ebss_l2; | ||
| 180 | r2.h = __ebss_l2; | ||
| 181 | call __init_clear_bss | ||
| 182 | #endif | ||
| 183 | r1.l = ___bss_start; | ||
| 184 | r1.h = ___bss_start; | ||
| 185 | r2.l = ___bss_stop; | ||
| 186 | r2.h = ___bss_stop; | ||
| 187 | call __init_clear_bss | ||
| 188 | |||
| 147 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ | 189 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ |
| 148 | call _bfin_relocate_l1_mem; | 190 | call _bfin_relocate_l1_mem; |
| 149 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | 191 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
| @@ -185,19 +227,6 @@ ENDPROC(__start) | |||
| 185 | # define WDOG_CTL WDOGA_CTL | 227 | # define WDOG_CTL WDOGA_CTL |
| 186 | #endif | 228 | #endif |
| 187 | 229 | ||
| 188 | ENTRY(__init_clear_bss) | ||
| 189 | r2 = r2 - r1; | ||
| 190 | cc = r2 == 0; | ||
| 191 | if cc jump .L_bss_done; | ||
| 192 | r2 >>= 2; | ||
| 193 | p1 = r1; | ||
| 194 | p2 = r2; | ||
| 195 | lsetup (1f, 1f) lc0 = p2; | ||
| 196 | 1: [p1++] = r0; | ||
| 197 | .L_bss_done: | ||
| 198 | rts; | ||
| 199 | ENDPROC(__init_clear_bss) | ||
| 200 | |||
| 201 | ENTRY(_real_start) | 230 | ENTRY(_real_start) |
| 202 | /* Enable nested interrupts */ | 231 | /* Enable nested interrupts */ |
| 203 | [--sp] = reti; | 232 | [--sp] = reti; |
| @@ -209,35 +238,6 @@ ENTRY(_real_start) | |||
| 209 | w[p0] = r0; | 238 | w[p0] = r0; |
| 210 | ssync; | 239 | ssync; |
| 211 | 240 | ||
| 212 | r0 = 0 (x); | ||
| 213 | /* Zero out all of the fun bss regions */ | ||
| 214 | #if L1_DATA_A_LENGTH > 0 | ||
| 215 | r1.l = __sbss_l1; | ||
| 216 | r1.h = __sbss_l1; | ||
| 217 | r2.l = __ebss_l1; | ||
| 218 | r2.h = __ebss_l1; | ||
| 219 | call __init_clear_bss | ||
| 220 | #endif | ||
| 221 | #if L1_DATA_B_LENGTH > 0 | ||
| 222 | r1.l = __sbss_b_l1; | ||
| 223 | r1.h = __sbss_b_l1; | ||
| 224 | r2.l = __ebss_b_l1; | ||
| 225 | r2.h = __ebss_b_l1; | ||
| 226 | call __init_clear_bss | ||
| 227 | #endif | ||
| 228 | #if L2_LENGTH > 0 | ||
| 229 | r1.l = __sbss_l2; | ||
| 230 | r1.h = __sbss_l2; | ||
| 231 | r2.l = __ebss_l2; | ||
| 232 | r2.h = __ebss_l2; | ||
| 233 | call __init_clear_bss | ||
| 234 | #endif | ||
| 235 | r1.l = ___bss_start; | ||
| 236 | r1.h = ___bss_start; | ||
| 237 | r2.l = ___bss_stop; | ||
| 238 | r2.h = ___bss_stop; | ||
| 239 | call __init_clear_bss | ||
| 240 | |||
| 241 | /* Pass the u-boot arguments to the global value command line */ | 241 | /* Pass the u-boot arguments to the global value command line */ |
| 242 | R0 = R7; | 242 | R0 = R7; |
| 243 | call _cmdline_init; | 243 | call _cmdline_init; |
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 473df0f7fa78..43c4eb9acb65 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S | |||
| @@ -195,7 +195,7 @@ ENDPROC(_evt_ivhw) | |||
| 195 | /* Interrupt routine for evt2 (NMI). | 195 | /* Interrupt routine for evt2 (NMI). |
| 196 | * We don't actually use this, so just return. | 196 | * We don't actually use this, so just return. |
| 197 | * For inner circle type details, please see: | 197 | * For inner circle type details, please see: |
| 198 | * http://docs.blackfin.uclinux.org/doku.php?id=linux:nmi | 198 | * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:nmi |
| 199 | */ | 199 | */ |
| 200 | ENTRY(_evt_nmi) | 200 | ENTRY(_evt_nmi) |
| 201 | .weak _evt_nmi | 201 | .weak _evt_nmi |
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 1bba6030dce9..202494568c6c 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
| @@ -1101,10 +1101,9 @@ int __init init_arch_irq(void) | |||
| 1101 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | 1101 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
| 1102 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | 1102 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
| 1103 | 1103 | ||
| 1104 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ | 1104 | #ifdef SIC_IWR0 |
| 1105 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) | ||
| 1106 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); | 1105 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
| 1107 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) | 1106 | # ifdef SIC_IWR1 |
| 1108 | /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which | 1107 | /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which |
| 1109 | * will screw up the bootrom as it relies on MDMA0/1 waking it | 1108 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
| 1110 | * up from IDLE instructions. See this report for more info: | 1109 | * up from IDLE instructions. See this report for more info: |
| @@ -1114,10 +1113,8 @@ int __init init_arch_irq(void) | |||
| 1114 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | 1113 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); |
| 1115 | else | 1114 | else |
| 1116 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | 1115 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
| 1117 | #else | 1116 | # endif |
| 1118 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | 1117 | # ifdef SIC_IWR2 |
| 1119 | #endif | ||
| 1120 | # ifdef CONFIG_BF54x | ||
| 1121 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); | 1118 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
| 1122 | # endif | 1119 | # endif |
| 1123 | #else | 1120 | #else |
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index d3d70fd67c16..f48a6aebb49b 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c | |||
| @@ -82,10 +82,9 @@ void bfin_pm_suspend_standby_enter(void) | |||
| 82 | 82 | ||
| 83 | bfin_pm_standby_restore(); | 83 | bfin_pm_standby_restore(); |
| 84 | 84 | ||
| 85 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ | 85 | #ifdef SIC_IWR0 |
| 86 | defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x) | ||
| 87 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); | 86 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
| 88 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) | 87 | # ifdef SIC_IWR1 |
| 89 | /* BF52x system reset does not properly reset SIC_IWR1 which | 88 | /* BF52x system reset does not properly reset SIC_IWR1 which |
| 90 | * will screw up the bootrom as it relies on MDMA0/1 waking it | 89 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
| 91 | * up from IDLE instructions. See this report for more info: | 90 | * up from IDLE instructions. See this report for more info: |
| @@ -95,10 +94,8 @@ void bfin_pm_suspend_standby_enter(void) | |||
| 95 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | 94 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); |
| 96 | else | 95 | else |
| 97 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | 96 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
| 98 | #else | 97 | # endif |
| 99 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | 98 | # ifdef SIC_IWR2 |
| 100 | #endif | ||
| 101 | # ifdef CONFIG_BF54x | ||
| 102 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); | 99 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
| 103 | # endif | 100 | # endif |
| 104 | #else | 101 | #else |
