5 files changed, 28 insertions, 30 deletions

diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index da93d9207165..5998d8632a73 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -74,7 +74,7 @@
 
 /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
 #if ANOMALY_05000220 && \
-        ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \
-         (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB)))
+        ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \
+         (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK)))
 # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.
 #endif
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 70e3411f558c..85c658083279 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -141,7 +141,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
         sclk = get_sclk() / 1000;
 
 #if ANOMALY_05000273 || ANOMALY_05000274 || \
-        (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE))
+        (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
         min_cclk = sclk * 2;
 #else
         min_cclk = sclk;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 31fa313e81cf..5a4e7c7fd92c 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -1609,6 +1609,7 @@ ENTRY(_sys_call_table)
         .long _sys_preadv
         .long _sys_pwritev
         .long _sys_rt_tgsigqueueinfo
+        .long _sys_perf_counter_open
 
         .rept NR_syscalls-(.-_sys_call_table)/4
         .long _sys_ni_syscall
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index af70f09acd55..b42150190d0e 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1052,35 +1052,34 @@ int __init init_arch_irq(void)
                         set_irq_chained_handler(irq, bfin_demux_error_irq);
                         break;
 #endif
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
-                case IRQ_TIMER0:
-                        set_irq_handler(irq, handle_percpu_irq);
-                        break;
-#endif
 #ifdef CONFIG_SMP
                 case IRQ_SUPPLE_0:
                 case IRQ_SUPPLE_1:
                         set_irq_handler(irq, handle_percpu_irq);
                         break;
 #endif
-                default:
 #ifdef CONFIG_IPIPE
-                        /*
-                         * We want internal interrupt sources to be
-                         * masked, because ISRs may trigger interrupts
-                         * recursively (e.g. DMA), but interrupts are
-                         * _not_ masked at CPU level. So let's handle
-                         * most of them as level interrupts, except
-                         * the timer interrupt which is special.
-                         */
-                        if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR)
-                                set_irq_handler(irq, handle_simple_irq);
-                        else
-                                set_irq_handler(irq, handle_level_irq);
+#ifndef CONFIG_TICKSOURCE_CORETMR
+                case IRQ_TIMER0:
+                        set_irq_handler(irq, handle_simple_irq);
+                        break;
+#endif /* !CONFIG_TICKSOURCE_CORETMR */
+                case IRQ_CORETMR:
+                        set_irq_handler(irq, handle_simple_irq);
+                        break;
+                default:
+                        set_irq_handler(irq, handle_level_irq);
+                        break;
 #else /* !CONFIG_IPIPE */
+#ifdef CONFIG_TICKSOURCE_GPTMR0
+                case IRQ_TIMER0:
+                        set_irq_handler(irq, handle_percpu_irq);
+                        break;
+#endif /* CONFIG_TICKSOURCE_GPTMR0 */
+                default:
                         set_irq_handler(irq, handle_simple_irq);
-#endif /* !CONFIG_IPIPE */
                         break;
+#endif  /* !CONFIG_IPIPE */
                 }
         }
 
@@ -1224,15 +1223,14 @@ __attribute__((l1_text))
 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
 {
         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
-        struct ipipe_domain *this_domain = ipipe_current_domain;
+        struct ipipe_domain *this_domain = __ipipe_current_domain;
         struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
         int irq, s;
 
-        if (likely(vec == EVT_IVTMR_P)) {
+        if (likely(vec == EVT_IVTMR_P))
                 irq = IRQ_CORETMR;
-
-        } else {
+        else {
 #if defined(SIC_ISR0) || defined(SICA_ISR0)
                 unsigned long sic_status[3];
 
@@ -1262,12 +1260,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
                                 break;
                 }
 #endif
-
                 irq = ivg->irqno;
         }
 
         if (irq == IRQ_SYSTMR) {
-#ifndef CONFIG_GENERIC_CLOCKEVENTS
+#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
 #endif
                 /* This is basically what we need from the register frame. */
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index bce5a84be49f..9e7e27b7fc8d 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr)
         return 0;
 }
 
-#ifdef CONFIG_BFIN_WB
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
 static void flushinv_all_dcache(void)
 {
         u32 way, bank, subbank, set;
@@ -175,7 +175,7 @@ static inline void dcache_disable(void)
 #ifdef CONFIG_BFIN_DCACHE
         unsigned long ctrl;
 
-#ifdef CONFIG_BFIN_WB
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
         flushinv_all_dcache();
 #endif
         SSYNC();