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-rw-r--r--arch/blackfin/mach-common/Makefile2
-rw-r--r--arch/blackfin/mach-common/arch_checks.c60
-rw-r--r--arch/blackfin/mach-common/cache.S8
-rw-r--r--arch/blackfin/mach-common/cacheinit.S14
-rw-r--r--arch/blackfin/mach-common/cplbhdlr.S8
-rw-r--r--arch/blackfin/mach-common/cplbmgr.S56
-rw-r--r--arch/blackfin/mach-common/dpmc.S54
-rw-r--r--arch/blackfin/mach-common/entry.S268
-rw-r--r--arch/blackfin/mach-common/interrupt.S56
-rw-r--r--arch/blackfin/mach-common/ints-priority-dc.c13
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c17
-rw-r--r--arch/blackfin/mach-common/lock.S24
12 files changed, 388 insertions, 192 deletions
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 0279ede70392..4d7733dfd5de 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,7 +4,7 @@
4 4
5obj-y := \ 5obj-y := \
6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \ 6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
7 interrupt.o lock.o irqpanic.o 7 interrupt.o lock.o irqpanic.o arch_checks.o
8 8
9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o 10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
new file mode 100644
index 000000000000..2f6ce397780f
--- /dev/null
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -0,0 +1,60 @@
1/*
2 * File: arch/blackfin/mach-common/arch_checks.c
3 * Based on:
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
5 *
6 * Created: 25Jul07
7 * Description: Do some checking to make sure things are OK
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <asm/mach/anomaly.h>
31#include <asm/mach-common/clocks.h>
32
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34
35# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
36# error "VCO selected is more than maximum value. Please change the VCO multipler"
37# endif
38
39# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
40# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
41# endif
42
43# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
44# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
45# endif
46
47# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
48# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
49# endif
50
51# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
52# error "Please select sclk less than cclk"
53# endif
54
55#endif /* CONFIG_BFIN_KERNEL_CLOCK */
56
57#if (CONFIG_MEM_SIZE % 4)
58#error "SDRAM mem size must be multible of 4MB"
59#endif
60
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 7063795eb7c0..0521b1588204 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -79,8 +79,8 @@ ENTRY(_icache_invalidate)
79ENTRY(_invalidate_entire_icache) 79ENTRY(_invalidate_entire_icache)
80 [--SP] = ( R7:5); 80 [--SP] = ( R7:5);
81 81
82 P0.L = (IMEM_CONTROL & 0xFFFF); 82 P0.L = LO(IMEM_CONTROL);
83 P0.H = (IMEM_CONTROL >> 16); 83 P0.H = HI(IMEM_CONTROL);
84 R7 = [P0]; 84 R7 = [P0];
85 85
86 /* Clear the IMC bit , All valid bits in the instruction 86 /* Clear the IMC bit , All valid bits in the instruction
@@ -197,8 +197,8 @@ ENTRY(_invalidate_entire_dcache)
197ENTRY(_dcache_invalidate) 197ENTRY(_dcache_invalidate)
198 [--SP] = ( R7:6); 198 [--SP] = ( R7:6);
199 199
200 P0.L = (DMEM_CONTROL & 0xFFFF); 200 P0.L = LO(DMEM_CONTROL);
201 P0.H = (DMEM_CONTROL >> 16); 201 P0.H = HI(DMEM_CONTROL);
202 R7 = [P0]; 202 R7 = [P0];
203 203
204 /* Clear the DMC[1:0] bits, All valid bits in the data 204 /* Clear the DMC[1:0] bits, All valid bits in the data
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index 5be6b975ae4a..22fada0c1cb3 100644
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -38,13 +38,13 @@
38 38
39.text 39.text
40 40
41#ifdef ANOMALY_05000125 41#if ANOMALY_05000125
42#if defined(CONFIG_BLKFIN_CACHE) 42#if defined(CONFIG_BFIN_ICACHE)
43ENTRY(_bfin_write_IMEM_CONTROL) 43ENTRY(_bfin_write_IMEM_CONTROL)
44 44
45 /* Enable Instruction Cache */ 45 /* Enable Instruction Cache */
46 P0.l = (IMEM_CONTROL & 0xFFFF); 46 P0.l = LO(IMEM_CONTROL);
47 P0.h = (IMEM_CONTROL >> 16); 47 P0.h = HI(IMEM_CONTROL);
48 48
49 /* Anomaly 05000125 */ 49 /* Anomaly 05000125 */
50 CLI R1; 50 CLI R1;
@@ -58,10 +58,10 @@ ENTRY(_bfin_write_IMEM_CONTROL)
58ENDPROC(_bfin_write_IMEM_CONTROL) 58ENDPROC(_bfin_write_IMEM_CONTROL)
59#endif 59#endif
60 60
61#if defined(CONFIG_BLKFIN_DCACHE) 61#if defined(CONFIG_BFIN_DCACHE)
62ENTRY(_bfin_write_DMEM_CONTROL) 62ENTRY(_bfin_write_DMEM_CONTROL)
63 P0.l = (DMEM_CONTROL & 0xFFFF); 63 P0.l = LO(DMEM_CONTROL);
64 P0.h = (DMEM_CONTROL >> 16); 64 P0.h = HI(DMEM_CONTROL);
65 65
66 CLI R1; 66 CLI R1;
67 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ 67 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
diff --git a/arch/blackfin/mach-common/cplbhdlr.S b/arch/blackfin/mach-common/cplbhdlr.S
index 2f3c72c23997..2788532de72b 100644
--- a/arch/blackfin/mach-common/cplbhdlr.S
+++ b/arch/blackfin/mach-common/cplbhdlr.S
@@ -69,14 +69,14 @@ ENTRY(__cplb_hdr)
69 69
70.Lis_icplb_miss: 70.Lis_icplb_miss:
71 71
72#if defined(CONFIG_BLKFIN_CACHE) || defined(CONFIG_BLKFIN_DCACHE) 72#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
73# if defined(CONFIG_BLKFIN_CACHE) && !defined(CONFIG_BLKFIN_DCACHE) 73# if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE)
74 R1 = CPLB_ENABLE_ICACHE; 74 R1 = CPLB_ENABLE_ICACHE;
75# endif 75# endif
76# if !defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE) 76# if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
77 R1 = CPLB_ENABLE_DCACHE; 77 R1 = CPLB_ENABLE_DCACHE;
78# endif 78# endif
79# if defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE) 79# if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
80 R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; 80 R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
81# endif 81# endif
82#else 82#else
diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S
index e4b47e09cf13..946703ef48ff 100644
--- a/arch/blackfin/mach-common/cplbmgr.S
+++ b/arch/blackfin/mach-common/cplbmgr.S
@@ -75,15 +75,15 @@ ENTRY(_cplb_mgr)
75 * from the configuration table. 75 * from the configuration table.
76 */ 76 */
77 77
78 P4.L = (ICPLB_FAULT_ADDR & 0xFFFF); 78 P4.L = LO(ICPLB_FAULT_ADDR);
79 P4.H = (ICPLB_FAULT_ADDR >> 16); 79 P4.H = HI(ICPLB_FAULT_ADDR);
80 80
81 P1 = 16; 81 P1 = 16;
82 P5.L = _page_size_table; 82 P5.L = _page_size_table;
83 P5.H = _page_size_table; 83 P5.H = _page_size_table;
84 84
85 P0.L = (ICPLB_DATA0 & 0xFFFF); 85 P0.L = LO(ICPLB_DATA0);
86 P0.H = (ICPLB_DATA0 >> 16); 86 P0.H = HI(ICPLB_DATA0);
87 R4 = [P4]; /* Get faulting address*/ 87 R4 = [P4]; /* Get faulting address*/
88 R6 = 64; /* Advance past the fault address, which*/ 88 R6 = 64; /* Advance past the fault address, which*/
89 R6 = R6 + R4; /* we'll use if we find a match*/ 89 R6 = R6 + R4; /* we'll use if we find a match*/
@@ -117,13 +117,13 @@ ENTRY(_cplb_mgr)
117 I0 = R4; /* Fault address we'll search for*/ 117 I0 = R4; /* Fault address we'll search for*/
118 118
119 /* set up pointers */ 119 /* set up pointers */
120 P0.L = (ICPLB_DATA0 & 0xFFFF); 120 P0.L = LO(ICPLB_DATA0);
121 P0.H = (ICPLB_DATA0 >> 16); 121 P0.H = HI(ICPLB_DATA0);
122 122
123 /* The replacement procedure for ICPLBs */ 123 /* The replacement procedure for ICPLBs */
124 124
125 P4.L = (IMEM_CONTROL & 0xFFFF); 125 P4.L = LO(IMEM_CONTROL);
126 P4.H = (IMEM_CONTROL >> 16); 126 P4.H = HI(IMEM_CONTROL);
127 127
128 /* disable cplbs */ 128 /* disable cplbs */
129 R5 = [P4]; /* Control Register*/ 129 R5 = [P4]; /* Control Register*/
@@ -243,8 +243,8 @@ ENTRY(_cplb_mgr)
243 * last entry of the table. 243 * last entry of the table.
244 */ 244 */
245 245
246 P1.L = (ICPLB_DATA15 & 0xFFFF); /* ICPLB_DATA15 */ 246 P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */
247 P1.H = (ICPLB_DATA15 >> 16); 247 P1.H = HI(ICPLB_DATA15);
248 [P1] = R2; 248 [P1] = R2;
249 [P1-0x100] = R4; 249 [P1-0x100] = R4;
250#ifdef CONFIG_CPLB_INFO 250#ifdef CONFIG_CPLB_INFO
@@ -292,10 +292,10 @@ ENTRY(_cplb_mgr)
292 * pending writes associated with the CPLB. 292 * pending writes associated with the CPLB.
293 */ 293 */
294 294
295 P4.L = (DCPLB_STATUS & 0xFFFF); 295 P4.L = LO(DCPLB_STATUS);
296 P4.H = (DCPLB_STATUS >> 16); 296 P4.H = HI(DCPLB_STATUS);
297 P3.L = (DCPLB_DATA0 & 0xFFFF); 297 P3.L = LO(DCPLB_DATA0);
298 P3.H = (DCPLB_DATA0 >> 16); 298 P3.H = HI(DCPLB_DATA0);
299 R5 = [P4]; 299 R5 = [P4];
300 300
301 /* A protection violation can be caused by more than just writes 301 /* A protection violation can be caused by more than just writes
@@ -355,11 +355,11 @@ ENTRY(_cplb_mgr)
355 * config table, that covers the faulting address. 355 * config table, that covers the faulting address.
356 */ 356 */
357 357
358 P1.L = (DCPLB_DATA15 & 0xFFFF); 358 P1.L = LO(DCPLB_DATA15);
359 P1.H = (DCPLB_DATA15 >> 16); 359 P1.H = HI(DCPLB_DATA15);
360 360
361 P4.L = (DCPLB_FAULT_ADDR & 0xFFFF); 361 P4.L = LO(DCPLB_FAULT_ADDR);
362 P4.H = (DCPLB_FAULT_ADDR >> 16); 362 P4.H = HI(DCPLB_FAULT_ADDR);
363 R4 = [P4]; 363 R4 = [P4];
364 I0 = R4; 364 I0 = R4;
365 365
@@ -368,8 +368,8 @@ ENTRY(_cplb_mgr)
368 R6 = R1; /* Save for later*/ 368 R6 = R1; /* Save for later*/
369 369
370 /* Turn off CPLBs while we work.*/ 370 /* Turn off CPLBs while we work.*/
371 P4.L = (DMEM_CONTROL & 0xFFFF); 371 P4.L = LO(DMEM_CONTROL);
372 P4.H = (DMEM_CONTROL >> 16); 372 P4.H = HI(DMEM_CONTROL);
373 R5 = [P4]; 373 R5 = [P4];
374 BITCLR(R5,ENDCPLB_P); 374 BITCLR(R5,ENDCPLB_P);
375 CLI R0; 375 CLI R0;
@@ -384,8 +384,8 @@ ENTRY(_cplb_mgr)
384 * are no good. 384 * are no good.
385 */ 385 */
386 386
387 I1.L = (DCPLB_DATA0 & 0xFFFF); 387 I1.L = LO(DCPLB_DATA0);
388 I1.H = (DCPLB_DATA0 >> 16); 388 I1.H = HI(DCPLB_DATA0);
389 P1 = 2; 389 P1 = 2;
390 P2 = 16; 390 P2 = 16;
391 I2.L = _dcplb_preference; 391 I2.L = _dcplb_preference;
@@ -405,7 +405,7 @@ ENTRY(_cplb_mgr)
405 P3.L = _page_size_table; /* retrieve end address */ 405 P3.L = _page_size_table; /* retrieve end address */
406 P3.H = _page_size_table; /* retrieve end address */ 406 P3.H = _page_size_table; /* retrieve end address */
407 R3 = 0x1002; /* 16th - position, 2 bits -length */ 407 R3 = 0x1002; /* 16th - position, 2 bits -length */
408#ifdef ANOMALY_05000209 408#if ANOMALY_05000209
409 nop; /* Anomaly 05000209 */ 409 nop; /* Anomaly 05000209 */
410#endif 410#endif
411 R7 = EXTRACT(R1,R3.l); 411 R7 = EXTRACT(R1,R3.l);
@@ -475,8 +475,8 @@ ENTRY(_cplb_mgr)
475 * one space closer to the start. 475 * one space closer to the start.
476 */ 476 */
477 477
478 R1.L = (DCPLB_DATA16 & 0xFFFF); /* DCPLB_DATA15 + 4 */ 478 R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */
479 R1.H = (DCPLB_DATA16 >> 16); 479 R1.H = HI(DCPLB_DATA16);
480 R0 = P0; 480 R0 = P0;
481 481
482 /* If the victim happens to be in DCPLB15, 482 /* If the victim happens to be in DCPLB15,
@@ -549,8 +549,8 @@ ENTRY(_cplb_mgr)
549 * if necessary. 549 * if necessary.
550 */ 550 */
551 551
552 P1.L = (DCPLB_DATA15 & 0xFFFF); 552 P1.L = LO(DCPLB_DATA15);
553 P1.H = (DCPLB_DATA15 >> 16); 553 P1.H = HI(DCPLB_DATA15);
554 554
555 /* If the DCPLB has cache bits set, but caching hasn't 555 /* If the DCPLB has cache bits set, but caching hasn't
556 * been enabled, then we want to mask off the cache-in-L1 556 * been enabled, then we want to mask off the cache-in-L1
@@ -565,7 +565,7 @@ ENTRY(_cplb_mgr)
565 * cost of first-write exceptions to mark the page as dirty. 565 * cost of first-write exceptions to mark the page as dirty.
566 */ 566 */
567 567
568#ifdef CONFIG_BLKFIN_WT 568#ifdef CONFIG_BFIN_WT
569 BITSET(R6, 14); /* Set WT*/ 569 BITSET(R6, 14); /* Set WT*/
570#endif 570#endif
571 571
diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index 97cdcd6a00d4..39fbc2861107 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -39,8 +39,8 @@ ENTRY(_unmask_wdog_wakeup_evt)
39 P0.H = hi(SICA_IWR1); 39 P0.H = hi(SICA_IWR1);
40 P0.L = lo(SICA_IWR1); 40 P0.L = lo(SICA_IWR1);
41#else 41#else
42 P0.h = (SIC_IWR >> 16); 42 P0.h = HI(SIC_IWR);
43 P0.l = (SIC_IWR & 0xFFFF); 43 P0.l = LO(SIC_IWR);
44#endif 44#endif
45 R7 = [P0]; 45 R7 = [P0];
46#if defined(CONFIG_BF561) 46#if defined(CONFIG_BF561)
@@ -60,11 +60,11 @@ ENTRY(_unmask_wdog_wakeup_evt)
60 */ 60 */
61 R7 = 0x0000(z); 61 R7 = 0x0000(z);
62#if defined(CONFIG_BF561) 62#if defined(CONFIG_BF561)
63 P0.h = (WDOGA_STAT >> 16); 63 P0.h = HI(WDOGA_STAT);
64 P0.l = (WDOGA_STAT & 0xFFFF); 64 P0.l = LO(WDOGA_STAT);
65#else 65#else
66 P0.h = (WDOG_STAT >> 16); 66 P0.h = HI(WDOG_STAT);
67 P0.l = (WDOG_STAT & 0xFFFF); 67 P0.l = LO(WDOG_STAT);
68#endif 68#endif
69 [P0] = R7; 69 [P0] = R7;
70 SSYNC; 70 SSYNC;
@@ -73,21 +73,21 @@ ENTRY(_unmask_wdog_wakeup_evt)
73ENTRY(_program_wdog_timer) 73ENTRY(_program_wdog_timer)
74 [--SP] = ( R7:0, P5:0 ); 74 [--SP] = ( R7:0, P5:0 );
75#if defined(CONFIG_BF561) 75#if defined(CONFIG_BF561)
76 P0.h = (WDOGA_CNT >> 16); 76 P0.h = HI(WDOGA_CNT);
77 P0.l = (WDOGA_CNT & 0xFFFF); 77 P0.l = LO(WDOGA_CNT);
78#else 78#else
79 P0.h = (WDOG_CNT >> 16); 79 P0.h = HI(WDOG_CNT);
80 P0.l = (WDOG_CNT & 0xFFFF); 80 P0.l = LO(WDOG_CNT);
81#endif 81#endif
82 [P0] = R0; 82 [P0] = R0;
83 SSYNC; 83 SSYNC;
84 84
85#if defined(CONFIG_BF561) 85#if defined(CONFIG_BF561)
86 P0.h = (WDOGA_CTL >> 16); 86 P0.h = HI(WDOGA_CTL);
87 P0.l = (WDOGA_CTL & 0xFFFF); 87 P0.l = LO(WDOGA_CTL);
88#else 88#else
89 P0.h = (WDOG_CTL >> 16); 89 P0.h = HI(WDOG_CTL);
90 P0.l = (WDOG_CTL & 0xFFFF); 90 P0.l = LO(WDOG_CTL);
91#endif 91#endif
92 R7 = W[P0](Z); 92 R7 = W[P0](Z);
93 CC = BITTST(R7,1); 93 CC = BITTST(R7,1);
@@ -97,11 +97,11 @@ ENTRY(_program_wdog_timer)
97 97
98.LSKIP_WRITE_TO_STAT: 98.LSKIP_WRITE_TO_STAT:
99#if defined(CONFIG_BF561) 99#if defined(CONFIG_BF561)
100 P0.h = (WDOGA_CTL >> 16); 100 P0.h = HI(WDOGA_CTL);
101 P0.l = (WDOGA_CTL & 0xFFFF); 101 P0.l = LO(WDOGA_CTL);
102#else 102#else
103 P0.h = (WDOG_CTL >> 16); 103 P0.h = HI(WDOG_CTL);
104 P0.l = (WDOG_CTL & 0xFFFF); 104 P0.l = LO(WDOG_CTL);
105#endif 105#endif
106 R7 = W[P0](Z); 106 R7 = W[P0](Z);
107 BITCLR(R7,1); /* Enable GP event */ 107 BITCLR(R7,1); /* Enable GP event */
@@ -122,11 +122,11 @@ ENTRY(_clear_wdog_wakeup_evt)
122 [--SP] = ( R7:0, P5:0 ); 122 [--SP] = ( R7:0, P5:0 );
123 123
124#if defined(CONFIG_BF561) 124#if defined(CONFIG_BF561)
125 P0.h = (WDOGA_CTL >> 16); 125 P0.h = HI(WDOGA_CTL);
126 P0.l = (WDOGA_CTL & 0xFFFF); 126 P0.l = LO(WDOGA_CTL);
127#else 127#else
128 P0.h = (WDOG_CTL >> 16); 128 P0.h = HI(WDOG_CTL);
129 P0.l = (WDOG_CTL & 0xFFFF); 129 P0.l = LO(WDOG_CTL);
130#endif 130#endif
131 R7 = 0x0AD6(Z); 131 R7 = 0x0AD6(Z);
132 W[P0] = R7.L; 132 W[P0] = R7.L;
@@ -149,11 +149,11 @@ ENTRY(_clear_wdog_wakeup_evt)
149ENTRY(_disable_wdog_timer) 149ENTRY(_disable_wdog_timer)
150 [--SP] = ( R7:0, P5:0 ); 150 [--SP] = ( R7:0, P5:0 );
151#if defined(CONFIG_BF561) 151#if defined(CONFIG_BF561)
152 P0.h = (WDOGA_CTL >> 16); 152 P0.h = HI(WDOGA_CTL);
153 P0.l = (WDOGA_CTL & 0xFFFF); 153 P0.l = LO(WDOGA_CTL);
154#else 154#else
155 P0.h = (WDOG_CTL >> 16); 155 P0.h = HI(WDOG_CTL);
156 P0.l = (WDOG_CTL & 0xFFFF); 156 P0.l = LO(WDOG_CTL);
157#endif 157#endif
158 R7 = 0xAD6(Z); 158 R7 = 0xAD6(Z);
159 W[P0] = R7.L; 159 W[P0] = R7.L;
@@ -300,7 +300,7 @@ ENTRY(_sleep_deeper)
300 P0.H = hi(PLL_CTL); 300 P0.H = hi(PLL_CTL);
301 P0.L = lo(PLL_CTL); 301 P0.L = lo(PLL_CTL);
302 R5 = W[P0](z); 302 R5 = W[P0](z);
303 R0.L = (MIN_VC/CONFIG_CLKIN_HZ) << 9; 303 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
304 W[P0] = R0.l; 304 W[P0] = R0.l;
305 305
306 SSYNC; 306 SSYNC;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 960458808344..e3ad5802868a 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -29,21 +29,7 @@
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */ 30 */
31 31
32/* 32/* NOTE: This code handles signal-recognition, which happens every time
33 * 25-Dec-2004 - LG Soft India
34 * 1. Fix in return_from_int, to make sure any pending
35 * system call in ILAT for this process to get
36 * executed, otherwise in case context switch happens,
37 * system call of first process (i.e in ILAT) will be
38 * carried forward to the switched process.
39 * 2. Removed Constant references for the following
40 * a. IPEND
41 * b. EXCAUSE mask
42 * c. PAGE Mask
43 */
44
45/*
46 * NOTE: This code handles signal-recognition, which happens every time
47 * after a timer-interrupt and after each system call. 33 * after a timer-interrupt and after each system call.
48 */ 34 */
49 35
@@ -58,6 +44,23 @@
58 44
59#include <asm/mach-common/context.S> 45#include <asm/mach-common/context.S>
60 46
47#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
48# define EX_SCRATCH_REG RETN
49#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
50# define EX_SCRATCH_REG RETE
51#else
52# define EX_SCRATCH_REG CYCLES
53#endif
54
55#if ANOMALY_05000281
56ENTRY(_safe_speculative_execution)
57 NOP;
58 NOP;
59 NOP;
60 jump _safe_speculative_execution;
61ENDPROC(_safe_speculative_execution)
62#endif
63
61#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 64#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
62.section .l1.text 65.section .l1.text
63#else 66#else
@@ -69,7 +72,7 @@
69 * patch up CPLB misses on the kernel stack. 72 * patch up CPLB misses on the kernel stack.
70 */ 73 */
71ENTRY(_ex_dcplb) 74ENTRY(_ex_dcplb)
72#if defined(ANOMALY_05000261) 75#if ANOMALY_05000261
73 /* 76 /*
74 * Work around an anomaly: if we see a new DCPLB fault, return 77 * Work around an anomaly: if we see a new DCPLB fault, return
75 * without doing anything. Then, if we get the same fault again, 78 * without doing anything. Then, if we get the same fault again,
@@ -93,7 +96,7 @@ ENTRY(_ex_icplb)
93 call __cplb_hdr; 96 call __cplb_hdr;
94 DEBUG_START_HWTRACE(p5, r7) 97 DEBUG_START_HWTRACE(p5, r7)
95 RESTORE_ALL_SYS 98 RESTORE_ALL_SYS
96 SP = RETN; 99 SP = EX_SCRATCH_REG;
97 rtx; 100 rtx;
98ENDPROC(_ex_icplb) 101ENDPROC(_ex_icplb)
99 102
@@ -102,7 +105,7 @@ ENTRY(_ex_syscall)
102 (R7:6,P5:4) = [sp++]; 105 (R7:6,P5:4) = [sp++];
103 ASTAT = [sp++]; 106 ASTAT = [sp++];
104 raise 15; /* invoked by TRAP #0, for sys call */ 107 raise 15; /* invoked by TRAP #0, for sys call */
105 sp = retn; 108 sp = EX_SCRATCH_REG;
106 rtx 109 rtx
107ENDPROC(_ex_syscall) 110ENDPROC(_ex_syscall)
108 111
@@ -135,9 +138,9 @@ ENTRY(_ex_single_step)
135 cc = r6 == r7; 138 cc = r6 == r7;
136 if !cc jump _ex_trap_c; 139 if !cc jump _ex_trap_c;
137 140
138_return_from_exception: 141ENTRY(_return_from_exception)
139 DEBUG_START_HWTRACE(p5, r7) 142 DEBUG_START_HWTRACE(p5, r7)
140#ifdef ANOMALY_05000257 143#if ANOMALY_05000257
141 R7=LC0; 144 R7=LC0;
142 LC0=R7; 145 LC0=R7;
143 R7=LC1; 146 R7=LC1;
@@ -145,7 +148,7 @@ _return_from_exception:
145#endif 148#endif
146 (R7:6,P5:4) = [sp++]; 149 (R7:6,P5:4) = [sp++];
147 ASTAT = [sp++]; 150 ASTAT = [sp++];
148 sp = retn; 151 sp = EX_SCRATCH_REG;
149 rtx; 152 rtx;
150ENDPROC(_ex_soft_bp) 153ENDPROC(_ex_soft_bp)
151 154
@@ -163,7 +166,17 @@ ENTRY(_handle_bad_cplb)
163 [--sp] = ASTAT; 166 [--sp] = ASTAT;
164 [--sp] = (R7:6, P5:4); 167 [--sp] = (R7:6, P5:4);
165 168
169ENTRY(_ex_replaceable)
170 nop;
171
166ENTRY(_ex_trap_c) 172ENTRY(_ex_trap_c)
173 /* Make sure we are not in a double fault */
174 p4.l = lo(IPEND);
175 p4.h = hi(IPEND);
176 r7 = [p4];
177 CC = BITTST (r7, 5);
178 if CC jump _double_fault;
179
167 /* Call C code (trap_c) to handle the exception, which most 180 /* Call C code (trap_c) to handle the exception, which most
168 * likely involves sending a signal to the current process. 181 * likely involves sending a signal to the current process.
169 * To avoid double faults, lower our priority to IRQ5 first. 182 * To avoid double faults, lower our priority to IRQ5 first.
@@ -204,11 +217,57 @@ ENTRY(_ex_trap_c)
204 DEBUG_START_HWTRACE(p5, r7) 217 DEBUG_START_HWTRACE(p5, r7)
205 (R7:6,P5:4) = [sp++]; 218 (R7:6,P5:4) = [sp++];
206 ASTAT = [sp++]; 219 ASTAT = [sp++];
207 SP = RETN; 220 SP = EX_SCRATCH_REG;
208 raise 5; 221 raise 5;
209 rtx; 222 rtx;
210ENDPROC(_ex_trap_c) 223ENDPROC(_ex_trap_c)
211 224
225/* We just realized we got an exception, while we were processing a different
226 * exception. This is a unrecoverable event, so crash
227 */
228ENTRY(_double_fault)
229 /* Turn caches & protection off, to ensure we don't get any more
230 * double exceptions
231 */
232
233 P4.L = LO(IMEM_CONTROL);
234 P4.H = HI(IMEM_CONTROL);
235
236 R5 = [P4]; /* Control Register*/
237 BITCLR(R5,ENICPLB_P);
238 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
239 .align 8;
240 [P4] = R5;
241 SSYNC;
242
243 P4.L = LO(DMEM_CONTROL);
244 P4.H = HI(DMEM_CONTROL);
245 R5 = [P4];
246 BITCLR(R5,ENDCPLB_P);
247 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
248 .align 8;
249 [P4] = R5;
250 SSYNC;
251
252 /* Fix up the stack */
253 (R7:6,P5:4) = [sp++];
254 ASTAT = [sp++];
255 SP = EX_SCRATCH_REG;
256
257 /* We should be out of the exception stack, and back down into
258 * kernel or user space stack
259 */
260 SAVE_ALL_SYS
261
262 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
263 SP += -12;
264 call _double_fault_c;
265 SP += 12;
266.L_double_fault_panic:
267 JUMP .L_double_fault_panic
268
269ENDPROC(_double_fault)
270
212ENTRY(_exception_to_level5) 271ENTRY(_exception_to_level5)
213 SAVE_ALL_SYS 272 SAVE_ALL_SYS
214 273
@@ -279,7 +338,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
279 * covered by a CPLB. Switch to an exception stack; use RETN as a 338 * covered by a CPLB. Switch to an exception stack; use RETN as a
280 * scratch register (for want of a better option). 339 * scratch register (for want of a better option).
281 */ 340 */
282 retn = sp; 341 EX_SCRATCH_REG = sp;
283 sp.l = _exception_stack_top; 342 sp.l = _exception_stack_top;
284 sp.h = _exception_stack_top; 343 sp.h = _exception_stack_top;
285 /* Try to deal with syscalls quickly. */ 344 /* Try to deal with syscalls quickly. */
@@ -290,8 +349,8 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
290 r6.l = lo(SEQSTAT_EXCAUSE); 349 r6.l = lo(SEQSTAT_EXCAUSE);
291 r6.h = hi(SEQSTAT_EXCAUSE); 350 r6.h = hi(SEQSTAT_EXCAUSE);
292 r7 = r7 & r6; 351 r7 = r7 & r6;
293 p5.h = _extable; 352 p5.h = _ex_table;
294 p5.l = _extable; 353 p5.l = _ex_table;
295 p4 = r7; 354 p4 = r7;
296 p5 = p5 + (p4 << 2); 355 p5 = p5 + (p4 << 2);
297 p4 = [p5]; 356 p4 = [p5];
@@ -634,9 +693,9 @@ ENTRY(_return_from_int)
634 p1.h = _schedule_and_signal_from_int; 693 p1.h = _schedule_and_signal_from_int;
635 [p0] = p1; 694 [p0] = p1;
636 csync; 695 csync;
637#if defined(ANOMALY_05000281) 696#if ANOMALY_05000281
638 r0.l = lo(CONFIG_BOOT_LOAD); 697 r0.l = _safe_speculative_execution;
639 r0.h = hi(CONFIG_BOOT_LOAD); 698 r0.h = _safe_speculative_execution;
640 reti = r0; 699 reti = r0;
641#endif 700#endif
642 r0 = 0x801f (z); 701 r0 = 0x801f (z);
@@ -648,9 +707,9 @@ ENTRY(_return_from_int)
648ENDPROC(_return_from_int) 707ENDPROC(_return_from_int)
649 708
650ENTRY(_lower_to_irq14) 709ENTRY(_lower_to_irq14)
651#if defined(ANOMALY_05000281) 710#if ANOMALY_05000281
652 r0.l = lo(CONFIG_BOOT_LOAD); 711 r0.l = _safe_speculative_execution;
653 r0.h = hi(CONFIG_BOOT_LOAD); 712 r0.h = _safe_speculative_execution;
654 reti = r0; 713 reti = r0;
655#endif 714#endif
656 r0 = 0x401f; 715 r0 = 0x401f;
@@ -731,6 +790,114 @@ ENTRY(_init_exception_buff)
731 rts; 790 rts;
732ENDPROC(_init_exception_buff) 791ENDPROC(_init_exception_buff)
733 792
793/* We handle this 100% in exception space - to reduce overhead
794 * Only potiential problem is if the software buffer gets swapped out of the
795 * CPLB table - then double fault. - so we don't let this happen in other places
796 */
797#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
798ENTRY(_ex_trace_buff_full)
799 [--sp] = P3;
800 [--sp] = P2;
801 [--sp] = LC0;
802 [--sp] = LT0;
803 [--sp] = LB0;
804 P5.L = _trace_buff_offset;
805 P5.H = _trace_buff_offset;
806 P3 = [P5]; /* trace_buff_offset */
807 P5.L = lo(TBUFSTAT);
808 P5.H = hi(TBUFSTAT);
809 R7 = [P5];
810 R7 <<= 1; /* double, since we need to read twice */
811 LC0 = R7;
812 R7 <<= 2; /* need to shift over again,
813 * to get the number of bytes */
814 P5.L = lo(TBUF);
815 P5.H = hi(TBUF);
816 R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1;
817
818 P2 = R7;
819 P3 = P3 + P2;
820 R7 = P3;
821 R7 = R7 & R6;
822 P3 = R7;
823 P2.L = _trace_buff_offset;
824 P2.H = _trace_buff_offset;
825 [P2] = P3;
826
827 P2.L = _software_trace_buff;
828 P2.H = _software_trace_buff;
829
830 LSETUP (.Lstart, .Lend) LC0;
831.Lstart:
832 R7 = [P5]; /* read TBUF */
833 P4 = P3 + P2;
834 [P4] = R7;
835 P3 += -4;
836 R7 = P3;
837 R7 = R7 & R6;
838.Lend:
839 P3 = R7;
840
841 LB0 = [sp++];
842 LT0 = [sp++];
843 LC0 = [sp++];
844 P2 = [sp++];
845 P3 = [sp++];
846 jump _return_from_exception;
847ENDPROC(_ex_trace_buff_full)
848
849#if CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN == 4
850.data
851#else
852.section .l1.data.B
853#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN */
854ENTRY(_trace_buff_offset)
855 .long 0;
856ALIGN
857ENTRY(_software_trace_buff)
858 .rept ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*256);
859 .long 0
860 .endr
861#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */
862
863#if CONFIG_EARLY_PRINTK
864.section .init.text
865ENTRY(_early_trap)
866 SAVE_ALL_SYS
867 trace_buffer_stop(p0,r0);
868
869 /* Turn caches off, to ensure we don't get double exceptions */
870
871 P4.L = LO(IMEM_CONTROL);
872 P4.H = HI(IMEM_CONTROL);
873
874 R5 = [P4]; /* Control Register*/
875 BITCLR(R5,ENICPLB_P);
876 CLI R1;
877 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
878 .align 8;
879 [P4] = R5;
880 SSYNC;
881
882 P4.L = LO(DMEM_CONTROL);
883 P4.H = HI(DMEM_CONTROL);
884 R5 = [P4];
885 BITCLR(R5,ENDCPLB_P);
886 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
887 .align 8;
888 [P4] = R5;
889 SSYNC;
890 STI R1;
891
892 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
893 r1 = RETX;
894
895 SP += -12;
896 call _early_trap_c;
897 SP += 12;
898ENDPROC(_early_trap)
899#endif /* CONFIG_EARLY_PRINTK */
900
734/* 901/*
735 * Put these in the kernel data section - that should always be covered by 902 * Put these in the kernel data section - that should always be covered by
736 * a CPLB. This is needed to ensure we don't get double fault conditions 903 * a CPLB. This is needed to ensure we don't get double fault conditions
@@ -741,30 +908,33 @@ ENDPROC(_init_exception_buff)
741#else 908#else
742.data 909.data
743#endif 910#endif
744ALIGN 911ENTRY(_ex_table)
745_extable:
746 /* entry for each EXCAUSE[5:0] 912 /* entry for each EXCAUSE[5:0]
747 * This table must be in sync with the table in ./kernel/traps.c 913 * This table must be in sync with the table in ./kernel/traps.c
748 * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined 914 * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
749 */ 915 */
750 .long _ex_syscall; /* 0x00 - User Defined - Linux Syscall */ 916 .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */
751 .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */ 917 .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */
752 .long _ex_trap_c /* 0x02 - User Defined */ 918 .long _ex_replaceable /* 0x02 - User Defined */
753 .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */ 919 .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
754 .long _ex_trap_c /* 0x04 - User Defined */ 920 .long _ex_replaceable /* 0x04 - User Defined */
755 .long _ex_trap_c /* 0x05 - User Defined */ 921 .long _ex_replaceable /* 0x05 - User Defined */
756 .long _ex_trap_c /* 0x06 - User Defined */ 922 .long _ex_replaceable /* 0x06 - User Defined */
757 .long _ex_trap_c /* 0x07 - User Defined */ 923 .long _ex_replaceable /* 0x07 - User Defined */
758 .long _ex_trap_c /* 0x08 - User Defined */ 924 .long _ex_replaceable /* 0x08 - User Defined */
759 .long _ex_trap_c /* 0x09 - User Defined */ 925 .long _ex_replaceable /* 0x09 - User Defined */
760 .long _ex_trap_c /* 0x0A - User Defined */ 926 .long _ex_replaceable /* 0x0A - User Defined */
761 .long _ex_trap_c /* 0x0B - User Defined */ 927 .long _ex_replaceable /* 0x0B - User Defined */
762 .long _ex_trap_c /* 0x0C - User Defined */ 928 .long _ex_replaceable /* 0x0C - User Defined */
763 .long _ex_trap_c /* 0x0D - User Defined */ 929 .long _ex_replaceable /* 0x0D - User Defined */
764 .long _ex_trap_c /* 0x0E - User Defined */ 930 .long _ex_replaceable /* 0x0E - User Defined */
765 .long _ex_trap_c /* 0x0F - User Defined */ 931 .long _ex_replaceable /* 0x0F - User Defined */
766 .long _ex_single_step /* 0x10 - HW Single step */ 932 .long _ex_single_step /* 0x10 - HW Single step */
933#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
934 .long _ex_trace_buff_full /* 0x11 - Trace Buffer Full */
935#else
767 .long _ex_trap_c /* 0x11 - Trace Buffer Full */ 936 .long _ex_trap_c /* 0x11 - Trace Buffer Full */
937#endif
768 .long _ex_trap_c /* 0x12 - Reserved */ 938 .long _ex_trap_c /* 0x12 - Reserved */
769 .long _ex_trap_c /* 0x13 - Reserved */ 939 .long _ex_trap_c /* 0x13 - Reserved */
770 .long _ex_trap_c /* 0x14 - Reserved */ 940 .long _ex_trap_c /* 0x14 - Reserved */
@@ -812,8 +982,8 @@ _extable:
812 .long _ex_trap_c /* 0x3D - Reserved */ 982 .long _ex_trap_c /* 0x3D - Reserved */
813 .long _ex_trap_c /* 0x3E - Reserved */ 983 .long _ex_trap_c /* 0x3E - Reserved */
814 .long _ex_trap_c /* 0x3F - Reserved */ 984 .long _ex_trap_c /* 0x3F - Reserved */
985END(_ex_table)
815 986
816ALIGN
817ENTRY(_sys_call_table) 987ENTRY(_sys_call_table)
818 .long _sys_restart_syscall /* 0 */ 988 .long _sys_restart_syscall /* 0 */
819 .long _sys_exit 989 .long _sys_exit
@@ -1184,7 +1354,7 @@ _exception_stack:
1184 .endr 1354 .endr
1185_exception_stack_top: 1355_exception_stack_top:
1186 1356
1187#if defined(ANOMALY_05000261) 1357#if ANOMALY_05000261
1188/* Used by the assembly entry point to work around an anomaly. */ 1358/* Used by the assembly entry point to work around an anomaly. */
1189_last_cplb_fault_retx: 1359_last_cplb_fault_retx:
1190 .long 0; 1360 .long 0;
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 203e20709163..c6b32fe0f6e9 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -46,30 +46,6 @@
46 46
47.align 4 /* just in case */ 47.align 4 /* just in case */
48 48
49/*
50 * initial interrupt handlers
51 */
52
53#ifndef CONFIG_KGDB
54 /* interrupt routine for emulation - 0 */
55 /* Currently used only if GDB stub is not in - invalid */
56 /* gdb-stub set the evt itself */
57 /* save registers for post-mortem only */
58ENTRY(_evt_emulation)
59 SAVE_ALL_SYS
60#ifdef CONFIG_FRAME_POINTER
61 fp = 0;
62#endif
63 r0 = IRQ_EMU;
64 r1 = sp;
65 SP += -12;
66 call _irq_panic;
67 SP += 12;
68 /* - GDB stub fills this in by itself (if defined) */
69 rte;
70ENDPROC(_evt_emulation)
71#endif
72
73/* Common interrupt entry code. First we do CLI, then push 49/* Common interrupt entry code. First we do CLI, then push
74 * RETI, to keep interrupts disabled, but to allow this state to be changed 50 * RETI, to keep interrupts disabled, but to allow this state to be changed
75 * by local_bh_enable. 51 * by local_bh_enable.
@@ -140,7 +116,7 @@ __common_int_entry:
140 fp = 0; 116 fp = 0;
141#endif 117#endif
142 118
143#if defined (ANOMALY_05000283) || defined (ANOMALY_05000315) 119#if ANOMALY_05000283 || ANOMALY_05000315
144 cc = r7 == r7; 120 cc = r7 == r7;
145 p5.h = 0xffc0; 121 p5.h = 0xffc0;
146 p5.l = 0x0014; 122 p5.l = 0x0014;
@@ -163,7 +139,7 @@ ENTRY(_evt_ivhw)
163#ifdef CONFIG_FRAME_POINTER 139#ifdef CONFIG_FRAME_POINTER
164 fp = 0; 140 fp = 0;
165#endif 141#endif
166#ifdef ANOMALY_05000283 142#if ANOMALY_05000283
167 cc = r7 == r7; 143 cc = r7 == r7;
168 p5.h = 0xffc0; 144 p5.h = 0xffc0;
169 p5.l = 0x0014; 145 p5.l = 0x0014;
@@ -201,27 +177,15 @@ ENTRY(_evt_ivhw)
201 jump .Lcommon_restore_context; 177 jump .Lcommon_restore_context;
202#endif 178#endif
203 179
204/* interrupt routine for evt2 - 2. This is NMI. */ 180/* Interrupt routine for evt2 (NMI).
205ENTRY(_evt_evt2) 181 * We don't actually use this, so just return.
206 SAVE_CONTEXT 182 * For inner circle type details, please see:
207#ifdef CONFIG_FRAME_POINTER 183 * http://docs.blackfin.uclinux.org/doku.php?id=linux:nmi
208 fp = 0; 184 */
209#endif 185ENTRY(_evt_nmi)
210#ifdef ANOMALY_05000283 186.weak _evt_nmi
211 cc = r7 == r7;
212 p5.h = 0xffc0;
213 p5.l = 0x0014;
214 if cc jump 1f;
215 r7.l = W[p5];
2161:
217#endif
218 r0 = IRQ_NMI;
219 r1 = sp;
220 SP += -12;
221 call _asm_do_IRQ;
222 SP += 12;
223 RESTORE_CONTEXT
224 rtn; 187 rtn;
188ENDPROC(_evt_nmi)
225 189
226/* interrupt routine for core timer - 6 */ 190/* interrupt routine for core timer - 6 */
227ENTRY(_evt_timer) 191ENTRY(_evt_timer)
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 660f881b620a..2db3546fc874 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -221,7 +221,7 @@ static unsigned int bf561_gpio_irq_startup(unsigned int irq)
221 221
222 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 222 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
223 223
224 ret = gpio_request(gpionr, NULL); 224 ret = gpio_request(gpionr, "IRQ");
225 if (ret) 225 if (ret)
226 return ret; 226 return ret;
227 227
@@ -261,7 +261,7 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
261 261
262 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 262 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
263 263
264 ret = gpio_request(gpionr, NULL); 264 ret = gpio_request(gpionr, "IRQ");
265 if (ret) 265 if (ret)
266 return ret; 266 return ret;
267 267
@@ -362,10 +362,11 @@ void __init init_exception_vectors(void)
362{ 362{
363 SSYNC(); 363 SSYNC();
364 364
365#ifndef CONFIG_KGDB 365 /* cannot program in software:
366 bfin_write_EVT0(evt_emulation); 366 * evt0 - emulation (jtag)
367#endif 367 * evt1 - reset
368 bfin_write_EVT2(evt_evt2); 368 */
369 bfin_write_EVT2(evt_nmi);
369 bfin_write_EVT3(trap); 370 bfin_write_EVT3(trap);
370 bfin_write_EVT5(evt_ivhw); 371 bfin_write_EVT5(evt_ivhw);
371 bfin_write_EVT6(evt_timer); 372 bfin_write_EVT6(evt_timer);
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 4708023fe716..d3b7672b2b94 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -343,7 +343,7 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
343 u16 gpionr = irq - IRQ_PF0; 343 u16 gpionr = irq - IRQ_PF0;
344 344
345 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 345 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
346 ret = gpio_request(gpionr, NULL); 346 ret = gpio_request(gpionr, "IRQ");
347 if (ret) 347 if (ret)
348 return ret; 348 return ret;
349 } 349 }
@@ -377,7 +377,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
377 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 377 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
378 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 378 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
379 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 379 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
380 ret = gpio_request(gpionr, NULL); 380 ret = gpio_request(gpionr, "IRQ");
381 if (ret) 381 if (ret)
382 return ret; 382 return ret;
383 } 383 }
@@ -587,7 +587,7 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
587 } 587 }
588 588
589 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 589 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
590 ret = gpio_request(gpionr, NULL); 590 ret = gpio_request(gpionr, "IRQ");
591 if (ret) 591 if (ret)
592 return ret; 592 return ret;
593 } 593 }
@@ -627,7 +627,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
627 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 627 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
628 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 628 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
629 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 629 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
630 ret = gpio_request(gpionr, NULL); 630 ret = gpio_request(gpionr, "IRQ");
631 if (ret) 631 if (ret)
632 return ret; 632 return ret;
633 } 633 }
@@ -721,10 +721,11 @@ void __init init_exception_vectors(void)
721{ 721{
722 SSYNC(); 722 SSYNC();
723 723
724#ifndef CONFIG_KGDB 724 /* cannot program in software:
725 bfin_write_EVT0(evt_emulation); 725 * evt0 - emulation (jtag)
726#endif 726 * evt1 - reset
727 bfin_write_EVT2(evt_evt2); 727 */
728 bfin_write_EVT2(evt_nmi);
728 bfin_write_EVT3(trap); 729 bfin_write_EVT3(trap);
729 bfin_write_EVT5(evt_ivhw); 730 bfin_write_EVT5(evt_ivhw);
730 bfin_write_EVT6(evt_timer); 731 bfin_write_EVT6(evt_timer);
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S
index 386ac8dda076..28b87fe9ce3c 100644
--- a/arch/blackfin/mach-common/lock.S
+++ b/arch/blackfin/mach-common/lock.S
@@ -33,7 +33,7 @@
33 33
34.text 34.text
35 35
36#ifdef CONFIG_BLKFIN_CACHE_LOCK 36#ifdef CONFIG_BFIN_ICACHE_LOCK
37 37
38/* When you come here, it is assumed that 38/* When you come here, it is assumed that
39 * R0 - Which way to be locked 39 * R0 - Which way to be locked
@@ -43,12 +43,12 @@ ENTRY(_cache_grab_lock)
43 43
44 [--SP]=( R7:0,P5:0 ); 44 [--SP]=( R7:0,P5:0 );
45 45
46 P1.H = (IMEM_CONTROL >> 16); 46 P1.H = HI(IMEM_CONTROL);
47 P1.L = (IMEM_CONTROL & 0xFFFF); 47 P1.L = LO(IMEM_CONTROL);
48 P5.H = (ICPLB_ADDR0 >> 16); 48 P5.H = HI(ICPLB_ADDR0);
49 P5.L = (ICPLB_ADDR0 & 0xFFFF); 49 P5.L = LO(ICPLB_ADDR0);
50 P4.H = (ICPLB_DATA0 >> 16); 50 P4.H = HI(ICPLB_DATA0);
51 P4.L = (ICPLB_DATA0 & 0xFFFF); 51 P4.L = LO(ICPLB_DATA0);
52 R7 = R0; 52 R7 = R0;
53 53
54 /* If the code of interest already resides in the cache 54 /* If the code of interest already resides in the cache
@@ -167,8 +167,8 @@ ENTRY(_cache_lock)
167 167
168 [--SP]=( R7:0,P5:0 ); 168 [--SP]=( R7:0,P5:0 );
169 169
170 P1.H = (IMEM_CONTROL >> 16); 170 P1.H = HI(IMEM_CONTROL);
171 P1.L = (IMEM_CONTROL & 0xFFFF); 171 P1.L = LO(IMEM_CONTROL);
172 172
173 /* Disable the Interrupts*/ 173 /* Disable the Interrupts*/
174 CLI R3; 174 CLI R3;
@@ -189,14 +189,14 @@ ENTRY(_cache_lock)
189 RTS; 189 RTS;
190ENDPROC(_cache_lock) 190ENDPROC(_cache_lock)
191 191
192#endif /* BLKFIN_CACHE_LOCK */ 192#endif /* BFIN_ICACHE_LOCK */
193 193
194/* Return the ILOC bits of IMEM_CONTROL 194/* Return the ILOC bits of IMEM_CONTROL
195 */ 195 */
196 196
197ENTRY(_read_iloc) 197ENTRY(_read_iloc)
198 P1.H = (IMEM_CONTROL >> 16); 198 P1.H = HI(IMEM_CONTROL);
199 P1.L = (IMEM_CONTROL & 0xFFFF); 199 P1.L = LO(IMEM_CONTROL);
200 R1 = 0xF; 200 R1 = 0xF;
201 R0 = [P1]; 201 R0 = [P1];
202 R0 = R0 >> 3; 202 R0 = R0 >> 3;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 01:37:14 -0500