diff options
Diffstat (limited to 'arch/blackfin/mach-common/ints-priority.c')
-rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 389c5e8aa456..6e808612d170 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
@@ -1052,7 +1052,7 @@ int __init init_arch_irq(void) | |||
1052 | set_irq_chained_handler(irq, bfin_demux_error_irq); | 1052 | set_irq_chained_handler(irq, bfin_demux_error_irq); |
1053 | break; | 1053 | break; |
1054 | #endif | 1054 | #endif |
1055 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | 1055 | #if defined(CONFIG_TICKSOURCE_GPTMR0) |
1056 | case IRQ_TIMER0: | 1056 | case IRQ_TIMER0: |
1057 | set_irq_handler(irq, handle_percpu_irq); | 1057 | set_irq_handler(irq, handle_percpu_irq); |
1058 | break; | 1058 | break; |
@@ -1232,13 +1232,9 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
1232 | 1232 | ||
1233 | if (likely(vec == EVT_IVTMR_P)) { | 1233 | if (likely(vec == EVT_IVTMR_P)) { |
1234 | irq = IRQ_CORETMR; | 1234 | irq = IRQ_CORETMR; |
1235 | goto core_tick; | ||
1236 | } | ||
1237 | |||
1238 | SSYNC(); | ||
1239 | 1235 | ||
1236 | } else { | ||
1240 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 1237 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) |
1241 | { | ||
1242 | unsigned long sic_status[3]; | 1238 | unsigned long sic_status[3]; |
1243 | 1239 | ||
1244 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); | 1240 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
@@ -1254,9 +1250,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
1254 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) | 1250 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
1255 | break; | 1251 | break; |
1256 | } | 1252 | } |
1257 | } | ||
1258 | #else | 1253 | #else |
1259 | { | ||
1260 | unsigned long sic_status; | 1254 | unsigned long sic_status; |
1261 | 1255 | ||
1262 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); | 1256 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
@@ -1268,15 +1262,13 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
1268 | } else if (sic_status & ivg->isrflag) | 1262 | } else if (sic_status & ivg->isrflag) |
1269 | break; | 1263 | break; |
1270 | } | 1264 | } |
1271 | } | ||
1272 | #endif | 1265 | #endif |
1273 | 1266 | ||
1274 | irq = ivg->irqno; | 1267 | irq = ivg->irqno; |
1268 | } | ||
1275 | 1269 | ||
1276 | if (irq == IRQ_SYSTMR) { | 1270 | if (irq == IRQ_SYSTMR) { |
1277 | #ifdef CONFIG_GENERIC_CLOCKEVENTS | 1271 | #ifndef CONFIG_GENERIC_CLOCKEVENTS |
1278 | core_tick: | ||
1279 | #else | ||
1280 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ | 1272 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ |
1281 | #endif | 1273 | #endif |
1282 | /* This is basically what we need from the register frame. */ | 1274 | /* This is basically what we need from the register frame. */ |
@@ -1288,9 +1280,6 @@ core_tick: | |||
1288 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; | 1280 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; |
1289 | } | 1281 | } |
1290 | 1282 | ||
1291 | #ifndef CONFIG_GENERIC_CLOCKEVENTS | ||
1292 | core_tick: | ||
1293 | #endif | ||
1294 | if (this_domain == ipipe_root_domain) { | 1283 | if (this_domain == ipipe_root_domain) { |
1295 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); | 1284 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); |
1296 | barrier(); | 1285 | barrier(); |
@@ -1308,7 +1297,7 @@ core_tick: | |||
1308 | } | 1297 | } |
1309 | } | 1298 | } |
1310 | 1299 | ||
1311 | return 0; | 1300 | return 0; |
1312 | } | 1301 | } |
1313 | 1302 | ||
1314 | #endif /* CONFIG_IPIPE */ | 1303 | #endif /* CONFIG_IPIPE */ |