diff options
Diffstat (limited to 'arch/blackfin/mach-common/ints-priority.c')
-rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 43 |
1 files changed, 20 insertions, 23 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 6cd52395a999..43d9fb195c1e 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
@@ -559,7 +559,7 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) | |||
559 | #ifdef CONFIG_IPIPE | 559 | #ifdef CONFIG_IPIPE |
560 | handle = handle_level_irq; | 560 | handle = handle_level_irq; |
561 | #endif | 561 | #endif |
562 | __set_irq_handler_unlocked(irq, handle); | 562 | __irq_set_handler_locked(irq, handle); |
563 | } | 563 | } |
564 | 564 | ||
565 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); | 565 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); |
@@ -578,10 +578,9 @@ static void bfin_gpio_ack_irq(struct irq_data *d) | |||
578 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) | 578 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) |
579 | { | 579 | { |
580 | unsigned int irq = d->irq; | 580 | unsigned int irq = d->irq; |
581 | struct irq_desc *desc = irq_to_desc(irq); | ||
582 | u32 gpionr = irq_to_gpio(irq); | 581 | u32 gpionr = irq_to_gpio(irq); |
583 | 582 | ||
584 | if (desc->handle_irq == handle_edge_irq) | 583 | if (!irqd_is_level_type(d)) |
585 | set_gpio_data(gpionr, 0); | 584 | set_gpio_data(gpionr, 0); |
586 | 585 | ||
587 | set_gpio_maska(gpionr, 0); | 586 | set_gpio_maska(gpionr, 0); |
@@ -837,12 +836,11 @@ void init_pint_lut(void) | |||
837 | 836 | ||
838 | static void bfin_gpio_ack_irq(struct irq_data *d) | 837 | static void bfin_gpio_ack_irq(struct irq_data *d) |
839 | { | 838 | { |
840 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
841 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; | 839 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
842 | u32 pintbit = PINT_BIT(pint_val); | 840 | u32 pintbit = PINT_BIT(pint_val); |
843 | u32 bank = PINT_2_BANK(pint_val); | 841 | u32 bank = PINT_2_BANK(pint_val); |
844 | 842 | ||
845 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | 843 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
846 | if (pint[bank]->invert_set & pintbit) | 844 | if (pint[bank]->invert_set & pintbit) |
847 | pint[bank]->invert_clear = pintbit; | 845 | pint[bank]->invert_clear = pintbit; |
848 | else | 846 | else |
@@ -854,12 +852,11 @@ static void bfin_gpio_ack_irq(struct irq_data *d) | |||
854 | 852 | ||
855 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) | 853 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) |
856 | { | 854 | { |
857 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
858 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; | 855 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
859 | u32 pintbit = PINT_BIT(pint_val); | 856 | u32 pintbit = PINT_BIT(pint_val); |
860 | u32 bank = PINT_2_BANK(pint_val); | 857 | u32 bank = PINT_2_BANK(pint_val); |
861 | 858 | ||
862 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | 859 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
863 | if (pint[bank]->invert_set & pintbit) | 860 | if (pint[bank]->invert_set & pintbit) |
864 | pint[bank]->invert_clear = pintbit; | 861 | pint[bank]->invert_clear = pintbit; |
865 | else | 862 | else |
@@ -1166,9 +1163,9 @@ int __init init_arch_irq(void) | |||
1166 | 1163 | ||
1167 | for (irq = 0; irq <= SYS_IRQS; irq++) { | 1164 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
1168 | if (irq <= IRQ_CORETMR) | 1165 | if (irq <= IRQ_CORETMR) |
1169 | set_irq_chip(irq, &bfin_core_irqchip); | 1166 | irq_set_chip(irq, &bfin_core_irqchip); |
1170 | else | 1167 | else |
1171 | set_irq_chip(irq, &bfin_internal_irqchip); | 1168 | irq_set_chip(irq, &bfin_internal_irqchip); |
1172 | 1169 | ||
1173 | switch (irq) { | 1170 | switch (irq) { |
1174 | #if defined(CONFIG_BF53x) | 1171 | #if defined(CONFIG_BF53x) |
@@ -1192,50 +1189,50 @@ int __init init_arch_irq(void) | |||
1192 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) | 1189 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
1193 | case IRQ_PORTF_INTA: | 1190 | case IRQ_PORTF_INTA: |
1194 | #endif | 1191 | #endif |
1195 | set_irq_chained_handler(irq, | 1192 | irq_set_chained_handler(irq, bfin_demux_gpio_irq); |
1196 | bfin_demux_gpio_irq); | ||
1197 | break; | 1193 | break; |
1198 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | 1194 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
1199 | case IRQ_GENERIC_ERROR: | 1195 | case IRQ_GENERIC_ERROR: |
1200 | set_irq_chained_handler(irq, bfin_demux_error_irq); | 1196 | irq_set_chained_handler(irq, bfin_demux_error_irq); |
1201 | break; | 1197 | break; |
1202 | #endif | 1198 | #endif |
1203 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | 1199 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
1204 | case IRQ_MAC_ERROR: | 1200 | case IRQ_MAC_ERROR: |
1205 | set_irq_chained_handler(irq, bfin_demux_mac_status_irq); | 1201 | irq_set_chained_handler(irq, |
1202 | bfin_demux_mac_status_irq); | ||
1206 | break; | 1203 | break; |
1207 | #endif | 1204 | #endif |
1208 | #ifdef CONFIG_SMP | 1205 | #ifdef CONFIG_SMP |
1209 | case IRQ_SUPPLE_0: | 1206 | case IRQ_SUPPLE_0: |
1210 | case IRQ_SUPPLE_1: | 1207 | case IRQ_SUPPLE_1: |
1211 | set_irq_handler(irq, handle_percpu_irq); | 1208 | irq_set_handler(irq, handle_percpu_irq); |
1212 | break; | 1209 | break; |
1213 | #endif | 1210 | #endif |
1214 | 1211 | ||
1215 | #ifdef CONFIG_TICKSOURCE_CORETMR | 1212 | #ifdef CONFIG_TICKSOURCE_CORETMR |
1216 | case IRQ_CORETMR: | 1213 | case IRQ_CORETMR: |
1217 | # ifdef CONFIG_SMP | 1214 | # ifdef CONFIG_SMP |
1218 | set_irq_handler(irq, handle_percpu_irq); | 1215 | irq_set_handler(irq, handle_percpu_irq); |
1219 | break; | 1216 | break; |
1220 | # else | 1217 | # else |
1221 | set_irq_handler(irq, handle_simple_irq); | 1218 | irq_set_handler(irq, handle_simple_irq); |
1222 | break; | 1219 | break; |
1223 | # endif | 1220 | # endif |
1224 | #endif | 1221 | #endif |
1225 | 1222 | ||
1226 | #ifdef CONFIG_TICKSOURCE_GPTMR0 | 1223 | #ifdef CONFIG_TICKSOURCE_GPTMR0 |
1227 | case IRQ_TIMER0: | 1224 | case IRQ_TIMER0: |
1228 | set_irq_handler(irq, handle_simple_irq); | 1225 | irq_set_handler(irq, handle_simple_irq); |
1229 | break; | 1226 | break; |
1230 | #endif | 1227 | #endif |
1231 | 1228 | ||
1232 | #ifdef CONFIG_IPIPE | 1229 | #ifdef CONFIG_IPIPE |
1233 | default: | 1230 | default: |
1234 | set_irq_handler(irq, handle_level_irq); | 1231 | irq_set_handler(irq, handle_level_irq); |
1235 | break; | 1232 | break; |
1236 | #else /* !CONFIG_IPIPE */ | 1233 | #else /* !CONFIG_IPIPE */ |
1237 | default: | 1234 | default: |
1238 | set_irq_handler(irq, handle_simple_irq); | 1235 | irq_set_handler(irq, handle_simple_irq); |
1239 | break; | 1236 | break; |
1240 | #endif /* !CONFIG_IPIPE */ | 1237 | #endif /* !CONFIG_IPIPE */ |
1241 | } | 1238 | } |
@@ -1243,22 +1240,22 @@ int __init init_arch_irq(void) | |||
1243 | 1240 | ||
1244 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | 1241 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
1245 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) | 1242 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) |
1246 | set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip, | 1243 | irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip, |
1247 | handle_level_irq); | 1244 | handle_level_irq); |
1248 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | 1245 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
1249 | set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); | 1246 | irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); |
1250 | #endif | 1247 | #endif |
1251 | #endif | 1248 | #endif |
1252 | 1249 | ||
1253 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | 1250 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
1254 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) | 1251 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) |
1255 | set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip, | 1252 | irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, |
1256 | handle_level_irq); | 1253 | handle_level_irq); |
1257 | #endif | 1254 | #endif |
1258 | /* if configured as edge, then will be changed to do_edge_IRQ */ | 1255 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
1259 | for (irq = GPIO_IRQ_BASE; | 1256 | for (irq = GPIO_IRQ_BASE; |
1260 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) | 1257 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) |
1261 | set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, | 1258 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, |
1262 | handle_level_irq); | 1259 | handle_level_irq); |
1263 | 1260 | ||
1264 | bfin_write_IMASK(0); | 1261 | bfin_write_IMASK(0); |