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-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c50
1 files changed, 45 insertions, 5 deletions
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 2cfc7d5aec5c..cec0f841fb5a 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -13,7 +13,7 @@
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> 13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola 14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl> 15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2006 Analog Devices Inc. 16 * Copyright 2004-2007 Analog Devices Inc.
17 * 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 * 19 *
@@ -65,9 +65,9 @@ atomic_t num_spurious;
65 65
66struct ivgx { 66struct ivgx {
67 /* irq number for request_irq, available in mach-bf533/irq.h */ 67 /* irq number for request_irq, available in mach-bf533/irq.h */
68 int irqno; 68 unsigned int irqno;
69 /* corresponding bit in the SIC_ISR register */ 69 /* corresponding bit in the SIC_ISR register */
70 int isrflag; 70 unsigned int isrflag;
71} ivg_table[NR_PERI_INTS]; 71} ivg_table[NR_PERI_INTS];
72 72
73struct ivg_slice { 73struct ivg_slice {
@@ -98,7 +98,7 @@ static void __init search_IAR(void)
98 bfin_read32((unsigned long *) SIC_IAR0 + 98 bfin_read32((unsigned long *) SIC_IAR0 +
99 (irqn >> 3)) >> iar_shift)) { 99 (irqn >> 3)) >> iar_shift)) {
100 ivg_table[irq_pos].irqno = IVG7 + irqn; 100 ivg_table[irq_pos].irqno = IVG7 + irqn;
101 ivg_table[irq_pos].isrflag = 1 << irqn; 101 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
102 ivg7_13[ivg].istop++; 102 ivg7_13[ivg].istop++;
103 irq_pos++; 103 irq_pos++;
104 } 104 }
@@ -141,15 +141,31 @@ static void bfin_core_unmask_irq(unsigned int irq)
141 141
142static void bfin_internal_mask_irq(unsigned int irq) 142static void bfin_internal_mask_irq(unsigned int irq)
143{ 143{
144#ifndef CONFIG_BF54x
144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 145 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
145 ~(1 << (irq - (IRQ_CORETMR + 1)))); 146 ~(1 << (irq - (IRQ_CORETMR + 1))));
147#else
148 unsigned mask_bank, mask_bit;
149 mask_bank = (irq - (IRQ_CORETMR +1))/32;
150 mask_bit = (irq - (IRQ_CORETMR + 1))%32;
151 bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \
152 ~(1 << mask_bit));
153#endif
146 SSYNC(); 154 SSYNC();
147} 155}
148 156
149static void bfin_internal_unmask_irq(unsigned int irq) 157static void bfin_internal_unmask_irq(unsigned int irq)
150{ 158{
159#ifndef CONFIG_BF54x
151 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 160 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
152 (1 << (irq - (IRQ_CORETMR + 1)))); 161 (1 << (irq - (IRQ_CORETMR + 1))));
162#else
163 unsigned mask_bank, mask_bit;
164 mask_bank = (irq - (IRQ_CORETMR +1))/32;
165 mask_bit = (irq - (IRQ_CORETMR + 1))%32;
166 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \
167 ( 1 << mask_bit));
168#endif
153 SSYNC(); 169 SSYNC();
154} 170}
155 171
@@ -452,7 +468,14 @@ int __init init_arch_irq(void)
452 int irq; 468 int irq;
453 unsigned long ilat = 0; 469 unsigned long ilat = 0;
454 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 470 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
471#ifdef CONFIG_BF54x
472 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
473 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
474 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
475#else
455 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 476 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
477#endif
478
456 SSYNC(); 479 SSYNC();
457 480
458 local_irq_disable(); 481 local_irq_disable();
@@ -555,9 +578,25 @@ void do_irq(int vec, struct pt_regs *fp)
555 } else { 578 } else {
556 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 579 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
557 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 580 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
558 unsigned long sic_status; 581#ifdef CONFIG_BF54x
582 unsigned long sic_status[3];
559 583
560 SSYNC(); 584 SSYNC();
585 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
586 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
587 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
588 SSYNC();
589 for(;; ivg++) {
590 if (ivg >= ivg_stop) {
591 atomic_inc(&num_spurious);
592 return;
593 }
594 if (sic_status[(ivg->irqno - IVG7)/32] & ivg->isrflag)
595 break;
596 }
597#else
598 unsigned long sic_status;
599 SSYNC();
561 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); 600 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
562 601
563 for (;; ivg++) { 602 for (;; ivg++) {
@@ -567,6 +606,7 @@ void do_irq(int vec, struct pt_regs *fp)
567 } else if (sic_status & ivg->isrflag) 606 } else if (sic_status & ivg->isrflag)
568 break; 607 break;
569 } 608 }
609#endif
570 vec = ivg->irqno; 610 vec = ivg->irqno;
571 } 611 }
572 asm_do_IRQ(vec, fp); 612 asm_do_IRQ(vec, fp);