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-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S600
1 files changed, 564 insertions, 36 deletions
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index b7981d31c392..46ee77afed20 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -7,7 +7,7 @@
7#include <linux/linkage.h> 7#include <linux/linkage.h>
8#include <asm/blackfin.h> 8#include <asm/blackfin.h>
9#include <asm/mach/irq.h> 9#include <asm/mach/irq.h>
10 10#include <asm/dpmc.h>
11 11
12.section .l1.text 12.section .l1.text
13 13
@@ -56,26 +56,25 @@ ENTRY(_hibernate_mode)
56 [--SP] = ( R7:0, P5:0 ); 56 [--SP] = ( R7:0, P5:0 );
57 [--SP] = RETS; 57 [--SP] = RETS;
58 58
59 R3 = R0;
60 R0 = IWR_DISABLE_ALL;
61 R1 = IWR_DISABLE_ALL;
62 R2 = IWR_DISABLE_ALL;
59 call _set_sic_iwr; 63 call _set_sic_iwr;
64 call _set_dram_srfs;
65 SSYNC;
60 66
61 R0 = 0xFFFF (Z); 67 R0 = 0xFFFF (Z);
62 call _set_rtc_istat; 68 call _set_rtc_istat;
63 69
64 P0.H = hi(VR_CTL); 70 P0.H = hi(VR_CTL);
65 P0.L = lo(VR_CTL); 71 P0.L = lo(VR_CTL);
66 R1 = W[P0](z);
67 BITSET (R1, 8);
68 BITCLR (R1, 0);
69 BITCLR (R1, 1);
70 W[P0] = R1.L;
71 SSYNC;
72 72
73 W[P0] = R3.L;
73 CLI R2; 74 CLI R2;
74 IDLE; 75 IDLE;
75 76.Lforever:
76 /* Actually, adding anything may not be necessary...SDRAM contents 77 jump .Lforever;
77 * are lost
78 */
79 78
80ENTRY(_deep_sleep) 79ENTRY(_deep_sleep)
81 [--SP] = ( R7:0, P5:0 ); 80 [--SP] = ( R7:0, P5:0 );
@@ -233,51 +232,70 @@ ENTRY(_sleep_deeper)
233 ( R7:0, P5:0 ) = [SP++]; 232 ( R7:0, P5:0 ) = [SP++];
234 RTS; 233 RTS;
235 234
235
236ENTRY(_set_dram_srfs) 236ENTRY(_set_dram_srfs)
237 /* set the dram to self refresh mode */ 237 /* set the dram to self refresh mode */
238#if defined(CONFIG_BF54x) 238 SSYNC;
239#if defined(EBIU_RSTCTL) /* DDR */
239 P0.H = hi(EBIU_RSTCTL); 240 P0.H = hi(EBIU_RSTCTL);
240 P0.L = lo(EBIU_RSTCTL); 241 P0.L = lo(EBIU_RSTCTL);
241 R2 = [P0]; 242 R2 = [P0];
242 R3.H = hi(SRREQ); 243 BITSET(R2, 3); /* SRREQ enter self-refresh mode */
243 R3.L = lo(SRREQ); 244 [P0] = R2;
244#else 245 SSYNC;
245 P0.H = hi(EBIU_SDGCTL); 2461:
247 R2 = [P0];
248 CC = BITTST(R2, 4);
249 if !CC JUMP 1b;
250#else /* SDRAM */
246 P0.L = lo(EBIU_SDGCTL); 251 P0.L = lo(EBIU_SDGCTL);
252 P0.H = hi(EBIU_SDGCTL);
247 R2 = [P0]; 253 R2 = [P0];
248 R3.H = hi(SRFS); 254 BITSET(R2, 24); /* SRFS enter self-refresh mode */
249 R3.L = lo(SRFS);
250#endif
251 R2 = R2|R3;
252 [P0] = R2; 255 [P0] = R2;
253 ssync; 256 SSYNC;
254#if defined(CONFIG_BF54x) 257
255.LSRR_MODE: 258 P0.L = lo(EBIU_SDSTAT);
259 P0.H = hi(EBIU_SDSTAT);
2601:
261 R2 = w[P0];
262 SSYNC;
263 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
264 if !cc jump 1b;
265
266 P0.L = lo(EBIU_SDGCTL);
267 P0.H = hi(EBIU_SDGCTL);
256 R2 = [P0]; 268 R2 = [P0];
257 CC = BITTST(R2, 4); 269 BITCLR(R2, 0); /* SCTLE disable CLKOUT */
258 if !CC JUMP .LSRR_MODE; 270 [P0] = R2;
259#endif 271#endif
260 RTS; 272 RTS;
261 273
274
262ENTRY(_unset_dram_srfs) 275ENTRY(_unset_dram_srfs)
263 /* set the dram out of self refresh mode */ 276 /* set the dram out of self refresh mode */
264#if defined(CONFIG_BF54x) 277#if defined(EBIU_RSTCTL) /* DDR */
265 P0.H = hi(EBIU_RSTCTL); 278 P0.H = hi(EBIU_RSTCTL);
266 P0.L = lo(EBIU_RSTCTL); 279 P0.L = lo(EBIU_RSTCTL);
267 R2 = [P0]; 280 R2 = [P0];
268 R3.H = hi(SRREQ); 281 BITCLR(R2, 3); /* clear SRREQ bit */
269 R3.L = lo(SRREQ); 282 [P0] = R2;
270#else 283#elif defined(EBIU_SDGCTL) /* SDRAM */
284
285 P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
271 P0.H = hi(EBIU_SDGCTL); 286 P0.H = hi(EBIU_SDGCTL);
272 P0.L = lo(EBIU_SDGCTL);
273 R2 = [P0]; 287 R2 = [P0];
274 R3.H = hi(SRFS); 288 BITSET(R2, 0); /* SCTLE enable CLKOUT */
275 R3.L = lo(SRFS); 289 [P0] = R2
290 SSYNC;
291
292 P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
293 P0.H = hi(EBIU_SDGCTL);
294 R2 = [P0];
295 BITCLR(R2, 24); /* clear SRFS bit */
296 [P0] = R2
276#endif 297#endif
277 R3 = ~R3; 298 SSYNC;
278 R2 = R2&R3;
279 [P0] = R2;
280 ssync;
281 RTS; 299 RTS;
282 300
283ENTRY(_set_sic_iwr) 301ENTRY(_set_sic_iwr)
@@ -307,6 +325,11 @@ ENTRY(_set_rtc_istat)
307 P0.L = lo(RTC_ISTAT); 325 P0.L = lo(RTC_ISTAT);
308 w[P0] = R0.L; 326 w[P0] = R0.L;
309 SSYNC; 327 SSYNC;
328#elif (ANOMALY_05000371)
329 nop;
330 nop;
331 nop;
332 nop;
310#endif 333#endif
311 RTS; 334 RTS;
312 335
@@ -318,3 +341,508 @@ ENTRY(_test_pll_locked)
318 CC = BITTST(R0,5); 341 CC = BITTST(R0,5);
319 IF !CC JUMP 1b; 342 IF !CC JUMP 1b;
320 RTS; 343 RTS;
344
345.section .text
346
347
348ENTRY(_do_hibernate)
349 [--SP] = ( R7:0, P5:0 );
350 [--SP] = RETS;
351 /* Save System MMRs */
352 R2 = R0;
353 P0.H = hi(PLL_CTL);
354 P0.L = lo(PLL_CTL);
355
356#ifdef SIC_IMASK0
357 PM_SYS_PUSH(SIC_IMASK0)
358#endif
359#ifdef SIC_IMASK1
360 PM_SYS_PUSH(SIC_IMASK1)
361#endif
362#ifdef SIC_IMASK2
363 PM_SYS_PUSH(SIC_IMASK2)
364#endif
365#ifdef SIC_IMASK
366 PM_SYS_PUSH(SIC_IMASK)
367#endif
368#ifdef SICA_IMASK0
369 PM_SYS_PUSH(SICA_IMASK0)
370#endif
371#ifdef SICA_IMASK1
372 PM_SYS_PUSH(SICA_IMASK1)
373#endif
374#ifdef SIC_IAR2
375 PM_SYS_PUSH(SIC_IAR0)
376 PM_SYS_PUSH(SIC_IAR1)
377 PM_SYS_PUSH(SIC_IAR2)
378#endif
379#ifdef SIC_IAR3
380 PM_SYS_PUSH(SIC_IAR3)
381#endif
382#ifdef SIC_IAR4
383 PM_SYS_PUSH(SIC_IAR4)
384 PM_SYS_PUSH(SIC_IAR5)
385 PM_SYS_PUSH(SIC_IAR6)
386#endif
387#ifdef SIC_IAR7
388 PM_SYS_PUSH(SIC_IAR7)
389#endif
390#ifdef SIC_IAR8
391 PM_SYS_PUSH(SIC_IAR8)
392 PM_SYS_PUSH(SIC_IAR9)
393 PM_SYS_PUSH(SIC_IAR10)
394 PM_SYS_PUSH(SIC_IAR11)
395#endif
396
397#ifdef SICA_IAR0
398 PM_SYS_PUSH(SICA_IAR0)
399 PM_SYS_PUSH(SICA_IAR1)
400 PM_SYS_PUSH(SICA_IAR2)
401 PM_SYS_PUSH(SICA_IAR3)
402 PM_SYS_PUSH(SICA_IAR4)
403 PM_SYS_PUSH(SICA_IAR5)
404 PM_SYS_PUSH(SICA_IAR6)
405 PM_SYS_PUSH(SICA_IAR7)
406#endif
407
408#ifdef SIC_IWR
409 PM_SYS_PUSH(SIC_IWR)
410#endif
411#ifdef SIC_IWR0
412 PM_SYS_PUSH(SIC_IWR0)
413#endif
414#ifdef SIC_IWR1
415 PM_SYS_PUSH(SIC_IWR1)
416#endif
417#ifdef SIC_IWR2
418 PM_SYS_PUSH(SIC_IWR2)
419#endif
420#ifdef SICA_IWR0
421 PM_SYS_PUSH(SICA_IWR0)
422#endif
423#ifdef SICA_IWR1
424 PM_SYS_PUSH(SICA_IWR1)
425#endif
426
427#ifdef PINT0_ASSIGN
428 PM_SYS_PUSH(PINT0_ASSIGN)
429 PM_SYS_PUSH(PINT1_ASSIGN)
430 PM_SYS_PUSH(PINT2_ASSIGN)
431 PM_SYS_PUSH(PINT3_ASSIGN)
432#endif
433
434 PM_SYS_PUSH(EBIU_AMBCTL0)
435 PM_SYS_PUSH(EBIU_AMBCTL1)
436 PM_SYS_PUSH16(EBIU_AMGCTL)
437
438#ifdef EBIU_FCTL
439 PM_SYS_PUSH(EBIU_MBSCTL)
440 PM_SYS_PUSH(EBIU_MODE)
441 PM_SYS_PUSH(EBIU_FCTL)
442#endif
443
444 PM_SYS_PUSH16(SYSCR)
445
446 /* Save Core MMRs */
447 P0.H = hi(SRAM_BASE_ADDRESS);
448 P0.L = lo(SRAM_BASE_ADDRESS);
449
450 PM_PUSH(DMEM_CONTROL)
451 PM_PUSH(DCPLB_ADDR0)
452 PM_PUSH(DCPLB_ADDR1)
453 PM_PUSH(DCPLB_ADDR2)
454 PM_PUSH(DCPLB_ADDR3)
455 PM_PUSH(DCPLB_ADDR4)
456 PM_PUSH(DCPLB_ADDR5)
457 PM_PUSH(DCPLB_ADDR6)
458 PM_PUSH(DCPLB_ADDR7)
459 PM_PUSH(DCPLB_ADDR8)
460 PM_PUSH(DCPLB_ADDR9)
461 PM_PUSH(DCPLB_ADDR10)
462 PM_PUSH(DCPLB_ADDR11)
463 PM_PUSH(DCPLB_ADDR12)
464 PM_PUSH(DCPLB_ADDR13)
465 PM_PUSH(DCPLB_ADDR14)
466 PM_PUSH(DCPLB_ADDR15)
467 PM_PUSH(DCPLB_DATA0)
468 PM_PUSH(DCPLB_DATA1)
469 PM_PUSH(DCPLB_DATA2)
470 PM_PUSH(DCPLB_DATA3)
471 PM_PUSH(DCPLB_DATA4)
472 PM_PUSH(DCPLB_DATA5)
473 PM_PUSH(DCPLB_DATA6)
474 PM_PUSH(DCPLB_DATA7)
475 PM_PUSH(DCPLB_DATA8)
476 PM_PUSH(DCPLB_DATA9)
477 PM_PUSH(DCPLB_DATA10)
478 PM_PUSH(DCPLB_DATA11)
479 PM_PUSH(DCPLB_DATA12)
480 PM_PUSH(DCPLB_DATA13)
481 PM_PUSH(DCPLB_DATA14)
482 PM_PUSH(DCPLB_DATA15)
483 PM_PUSH(IMEM_CONTROL)
484 PM_PUSH(ICPLB_ADDR0)
485 PM_PUSH(ICPLB_ADDR1)
486 PM_PUSH(ICPLB_ADDR2)
487 PM_PUSH(ICPLB_ADDR3)
488 PM_PUSH(ICPLB_ADDR4)
489 PM_PUSH(ICPLB_ADDR5)
490 PM_PUSH(ICPLB_ADDR6)
491 PM_PUSH(ICPLB_ADDR7)
492 PM_PUSH(ICPLB_ADDR8)
493 PM_PUSH(ICPLB_ADDR9)
494 PM_PUSH(ICPLB_ADDR10)
495 PM_PUSH(ICPLB_ADDR11)
496 PM_PUSH(ICPLB_ADDR12)
497 PM_PUSH(ICPLB_ADDR13)
498 PM_PUSH(ICPLB_ADDR14)
499 PM_PUSH(ICPLB_ADDR15)
500 PM_PUSH(ICPLB_DATA0)
501 PM_PUSH(ICPLB_DATA1)
502 PM_PUSH(ICPLB_DATA2)
503 PM_PUSH(ICPLB_DATA3)
504 PM_PUSH(ICPLB_DATA4)
505 PM_PUSH(ICPLB_DATA5)
506 PM_PUSH(ICPLB_DATA6)
507 PM_PUSH(ICPLB_DATA7)
508 PM_PUSH(ICPLB_DATA8)
509 PM_PUSH(ICPLB_DATA9)
510 PM_PUSH(ICPLB_DATA10)
511 PM_PUSH(ICPLB_DATA11)
512 PM_PUSH(ICPLB_DATA12)
513 PM_PUSH(ICPLB_DATA13)
514 PM_PUSH(ICPLB_DATA14)
515 PM_PUSH(ICPLB_DATA15)
516 PM_PUSH(EVT0)
517 PM_PUSH(EVT1)
518 PM_PUSH(EVT2)
519 PM_PUSH(EVT3)
520 PM_PUSH(EVT4)
521 PM_PUSH(EVT5)
522 PM_PUSH(EVT6)
523 PM_PUSH(EVT7)
524 PM_PUSH(EVT8)
525 PM_PUSH(EVT9)
526 PM_PUSH(EVT10)
527 PM_PUSH(EVT11)
528 PM_PUSH(EVT12)
529 PM_PUSH(EVT13)
530 PM_PUSH(EVT14)
531 PM_PUSH(EVT15)
532 PM_PUSH(IMASK)
533 PM_PUSH(ILAT)
534 PM_PUSH(IPRIO)
535 PM_PUSH(TCNTL)
536 PM_PUSH(TPERIOD)
537 PM_PUSH(TSCALE)
538 PM_PUSH(TCOUNT)
539 PM_PUSH(TBUFCTL)
540
541 /* Save Core Registers */
542 [--sp] = SYSCFG;
543 [--sp] = ( R7:0, P5:0 );
544 [--sp] = fp;
545 [--sp] = usp;
546
547 [--sp] = i0;
548 [--sp] = i1;
549 [--sp] = i2;
550 [--sp] = i3;
551
552 [--sp] = m0;
553 [--sp] = m1;
554 [--sp] = m2;
555 [--sp] = m3;
556
557 [--sp] = l0;
558 [--sp] = l1;
559 [--sp] = l2;
560 [--sp] = l3;
561
562 [--sp] = b0;
563 [--sp] = b1;
564 [--sp] = b2;
565 [--sp] = b3;
566 [--sp] = a0.x;
567 [--sp] = a0.w;
568 [--sp] = a1.x;
569 [--sp] = a1.w;
570
571 [--sp] = LC0;
572 [--sp] = LC1;
573 [--sp] = LT0;
574 [--sp] = LT1;
575 [--sp] = LB0;
576 [--sp] = LB1;
577
578 [--sp] = ASTAT;
579 [--sp] = CYCLES;
580 [--sp] = CYCLES2;
581
582 [--sp] = RETS;
583 r0 = RETI;
584 [--sp] = r0;
585 [--sp] = RETX;
586 [--sp] = RETN;
587 [--sp] = RETE;
588 [--sp] = SEQSTAT;
589
590 /* Save Magic, return address and Stack Pointer */
591 P0.H = 0;
592 P0.L = 0;
593 R0.H = 0xDEAD; /* Hibernate Magic */
594 R0.L = 0xBEEF;
595 [P0++] = R0; /* Store Hibernate Magic */
596 R0.H = pm_resume_here;
597 R0.L = pm_resume_here;
598 [P0++] = R0; /* Save Return Address */
599 [P0++] = SP; /* Save Stack Pointer */
600 P0.H = _hibernate_mode;
601 P0.L = _hibernate_mode;
602 R0 = R2;
603 call (P0); /* Goodbye */
604
605pm_resume_here:
606
607 /* Restore Core Registers */
608 SEQSTAT = [sp++];
609 RETE = [sp++];
610 RETN = [sp++];
611 RETX = [sp++];
612 r0 = [sp++];
613 RETI = r0;
614 RETS = [sp++];
615
616 CYCLES2 = [sp++];
617 CYCLES = [sp++];
618 ASTAT = [sp++];
619
620 LB1 = [sp++];
621 LB0 = [sp++];
622 LT1 = [sp++];
623 LT0 = [sp++];
624 LC1 = [sp++];
625 LC0 = [sp++];
626
627 a1.w = [sp++];
628 a1.x = [sp++];
629 a0.w = [sp++];
630 a0.x = [sp++];
631 b3 = [sp++];
632 b2 = [sp++];
633 b1 = [sp++];
634 b0 = [sp++];
635
636 l3 = [sp++];
637 l2 = [sp++];
638 l1 = [sp++];
639 l0 = [sp++];
640
641 m3 = [sp++];
642 m2 = [sp++];
643 m1 = [sp++];
644 m0 = [sp++];
645
646 i3 = [sp++];
647 i2 = [sp++];
648 i1 = [sp++];
649 i0 = [sp++];
650
651 usp = [sp++];
652 fp = [sp++];
653
654 ( R7 : 0, P5 : 0) = [ SP ++ ];
655 SYSCFG = [sp++];
656
657 /* Restore Core MMRs */
658
659 PM_POP(TBUFCTL)
660 PM_POP(TCOUNT)
661 PM_POP(TSCALE)
662 PM_POP(TPERIOD)
663 PM_POP(TCNTL)
664 PM_POP(IPRIO)
665 PM_POP(ILAT)
666 PM_POP(IMASK)
667 PM_POP(EVT15)
668 PM_POP(EVT14)
669 PM_POP(EVT13)
670 PM_POP(EVT12)
671 PM_POP(EVT11)
672 PM_POP(EVT10)
673 PM_POP(EVT9)
674 PM_POP(EVT8)
675 PM_POP(EVT7)
676 PM_POP(EVT6)
677 PM_POP(EVT5)
678 PM_POP(EVT4)
679 PM_POP(EVT3)
680 PM_POP(EVT2)
681 PM_POP(EVT1)
682 PM_POP(EVT0)
683 PM_POP(ICPLB_DATA15)
684 PM_POP(ICPLB_DATA14)
685 PM_POP(ICPLB_DATA13)
686 PM_POP(ICPLB_DATA12)
687 PM_POP(ICPLB_DATA11)
688 PM_POP(ICPLB_DATA10)
689 PM_POP(ICPLB_DATA9)
690 PM_POP(ICPLB_DATA8)
691 PM_POP(ICPLB_DATA7)
692 PM_POP(ICPLB_DATA6)
693 PM_POP(ICPLB_DATA5)
694 PM_POP(ICPLB_DATA4)
695 PM_POP(ICPLB_DATA3)
696 PM_POP(ICPLB_DATA2)
697 PM_POP(ICPLB_DATA1)
698 PM_POP(ICPLB_DATA0)
699 PM_POP(ICPLB_ADDR15)
700 PM_POP(ICPLB_ADDR14)
701 PM_POP(ICPLB_ADDR13)
702 PM_POP(ICPLB_ADDR12)
703 PM_POP(ICPLB_ADDR11)
704 PM_POP(ICPLB_ADDR10)
705 PM_POP(ICPLB_ADDR9)
706 PM_POP(ICPLB_ADDR8)
707 PM_POP(ICPLB_ADDR7)
708 PM_POP(ICPLB_ADDR6)
709 PM_POP(ICPLB_ADDR5)
710 PM_POP(ICPLB_ADDR4)
711 PM_POP(ICPLB_ADDR3)
712 PM_POP(ICPLB_ADDR2)
713 PM_POP(ICPLB_ADDR1)
714 PM_POP(ICPLB_ADDR0)
715 PM_POP(IMEM_CONTROL)
716 PM_POP(DCPLB_DATA15)
717 PM_POP(DCPLB_DATA14)
718 PM_POP(DCPLB_DATA13)
719 PM_POP(DCPLB_DATA12)
720 PM_POP(DCPLB_DATA11)
721 PM_POP(DCPLB_DATA10)
722 PM_POP(DCPLB_DATA9)
723 PM_POP(DCPLB_DATA8)
724 PM_POP(DCPLB_DATA7)
725 PM_POP(DCPLB_DATA6)
726 PM_POP(DCPLB_DATA5)
727 PM_POP(DCPLB_DATA4)
728 PM_POP(DCPLB_DATA3)
729 PM_POP(DCPLB_DATA2)
730 PM_POP(DCPLB_DATA1)
731 PM_POP(DCPLB_DATA0)
732 PM_POP(DCPLB_ADDR15)
733 PM_POP(DCPLB_ADDR14)
734 PM_POP(DCPLB_ADDR13)
735 PM_POP(DCPLB_ADDR12)
736 PM_POP(DCPLB_ADDR11)
737 PM_POP(DCPLB_ADDR10)
738 PM_POP(DCPLB_ADDR9)
739 PM_POP(DCPLB_ADDR8)
740 PM_POP(DCPLB_ADDR7)
741 PM_POP(DCPLB_ADDR6)
742 PM_POP(DCPLB_ADDR5)
743 PM_POP(DCPLB_ADDR4)
744 PM_POP(DCPLB_ADDR3)
745 PM_POP(DCPLB_ADDR2)
746 PM_POP(DCPLB_ADDR1)
747 PM_POP(DCPLB_ADDR0)
748 PM_POP(DMEM_CONTROL)
749
750 /* Restore System MMRs */
751
752 P0.H = hi(PLL_CTL);
753 P0.L = lo(PLL_CTL);
754 PM_SYS_POP16(SYSCR)
755
756#ifdef EBIU_FCTL
757 PM_SYS_POP(EBIU_FCTL)
758 PM_SYS_POP(EBIU_MODE)
759 PM_SYS_POP(EBIU_MBSCTL)
760#endif
761 PM_SYS_POP16(EBIU_AMGCTL)
762 PM_SYS_POP(EBIU_AMBCTL1)
763 PM_SYS_POP(EBIU_AMBCTL0)
764
765#ifdef PINT0_ASSIGN
766 PM_SYS_POP(PINT3_ASSIGN)
767 PM_SYS_POP(PINT2_ASSIGN)
768 PM_SYS_POP(PINT1_ASSIGN)
769 PM_SYS_POP(PINT0_ASSIGN)
770#endif
771
772#ifdef SICA_IWR1
773 PM_SYS_POP(SICA_IWR1)
774#endif
775#ifdef SICA_IWR0
776 PM_SYS_POP(SICA_IWR0)
777#endif
778#ifdef SIC_IWR2
779 PM_SYS_POP(SIC_IWR2)
780#endif
781#ifdef SIC_IWR1
782 PM_SYS_POP(SIC_IWR1)
783#endif
784#ifdef SIC_IWR0
785 PM_SYS_POP(SIC_IWR0)
786#endif
787#ifdef SIC_IWR
788 PM_SYS_POP(SIC_IWR)
789#endif
790
791#ifdef SICA_IAR0
792 PM_SYS_POP(SICA_IAR7)
793 PM_SYS_POP(SICA_IAR6)
794 PM_SYS_POP(SICA_IAR5)
795 PM_SYS_POP(SICA_IAR4)
796 PM_SYS_POP(SICA_IAR3)
797 PM_SYS_POP(SICA_IAR2)
798 PM_SYS_POP(SICA_IAR1)
799 PM_SYS_POP(SICA_IAR0)
800#endif
801
802#ifdef SIC_IAR8
803 PM_SYS_POP(SIC_IAR11)
804 PM_SYS_POP(SIC_IAR10)
805 PM_SYS_POP(SIC_IAR9)
806 PM_SYS_POP(SIC_IAR8)
807#endif
808#ifdef SIC_IAR7
809 PM_SYS_POP(SIC_IAR7)
810#endif
811#ifdef SIC_IAR6
812 PM_SYS_POP(SIC_IAR6)
813 PM_SYS_POP(SIC_IAR5)
814 PM_SYS_POP(SIC_IAR4)
815#endif
816#ifdef SIC_IAR3
817 PM_SYS_POP(SIC_IAR3)
818#endif
819#ifdef SIC_IAR2
820 PM_SYS_POP(SIC_IAR2)
821 PM_SYS_POP(SIC_IAR1)
822 PM_SYS_POP(SIC_IAR0)
823#endif
824#ifdef SICA_IMASK1
825 PM_SYS_POP(SICA_IMASK1)
826#endif
827#ifdef SICA_IMASK0
828 PM_SYS_POP(SICA_IMASK0)
829#endif
830#ifdef SIC_IMASK
831 PM_SYS_POP(SIC_IMASK)
832#endif
833#ifdef SIC_IMASK2
834 PM_SYS_POP(SIC_IMASK2)
835#endif
836#ifdef SIC_IMASK1
837 PM_SYS_POP(SIC_IMASK1)
838#endif
839#ifdef SIC_IMASK0
840 PM_SYS_POP(SIC_IMASK0)
841#endif
842
843 [--sp] = RETI; /* Clear Global Interrupt Disable */
844 SP += 4;
845
846 RETS = [SP++];
847 ( R7:0, P5:0 ) = [SP++];
848 RTS;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 18:00:24 -0500