1 files changed, 51 insertions, 23 deletions

diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index 39fbc2861107..b82c096e1980 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -38,6 +38,9 @@ ENTRY(_unmask_wdog_wakeup_evt)
 #if defined(CONFIG_BF561)
         P0.H = hi(SICA_IWR1);
         P0.L = lo(SICA_IWR1);
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+        P0.h = HI(SIC_IWR0);
+        P0.l = LO(SIC_IWR0);
 #else
         P0.h = HI(SIC_IWR);
         P0.l = LO(SIC_IWR);
@@ -172,7 +175,7 @@ ENTRY(_sleep_mode)
         call _set_sic_iwr;
 
         R0 = 0xFFFF (Z);
-        call _set_rtc_istat
+        call _set_rtc_istat;
 
         P0.H = hi(PLL_CTL);
         P0.L = lo(PLL_CTL);
@@ -210,7 +213,7 @@ ENTRY(_hibernate_mode)
         call _set_sic_iwr;
 
         R0 = 0xFFFF (Z);
-        call _set_rtc_istat
+        call _set_rtc_istat;
 
         P0.H = hi(VR_CTL);
         P0.L = lo(VR_CTL);
@@ -236,7 +239,7 @@ ENTRY(_deep_sleep)
 
         call _set_sic_iwr;
 
-        call _set_sdram_srfs;
+        call _set_dram_srfs;
 
         /* Clear all the interrupts,bits sticky */
         R0 = 0xFFFF (Z);
@@ -253,7 +256,7 @@ ENTRY(_deep_sleep)
         SSYNC;
         IDLE;
 
-        call _unset_sdram_srfs;
+        call _unset_dram_srfs;
 
         call _test_pll_locked;
 
@@ -285,23 +288,22 @@ ENTRY(_sleep_deeper)
         P3 = R0;
         R0 = IWR_ENABLE(0);
         call _set_sic_iwr;
-        call _set_sdram_srfs;
+        call _set_dram_srfs;    /* Set SDRAM Self Refresh */
 
         /* Clear all the interrupts,bits sticky */
         R0 = 0xFFFF (Z);
-        call _set_rtc_istat
-
+        call _set_rtc_istat;
         P0.H = hi(PLL_DIV);
         P0.L = lo(PLL_DIV);
         R6 = W[P0](z);
         R0.L = 0xF;
-        W[P0] = R0.l;
+        W[P0] = R0.l;           /* Set Max VCO to SCLK divider */
 
         P0.H = hi(PLL_CTL);
         P0.L = lo(PLL_CTL);
         R5 = W[P0](z);
         R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
-        W[P0] = R0.l;
+        W[P0] = R0.l;           /* Set Min CLKIN to VCO multiplier */
 
         SSYNC;
         IDLE;
@@ -317,29 +319,28 @@ ENTRY(_sleep_deeper)
         R1 = R1|R2;
 
         R2 = DEPOSIT(R7, R1);
-        W[P0] = R2;
+        W[P0] = R2;             /* Set Min Core Voltage */
 
         SSYNC;
         IDLE;
 
         call _test_pll_locked;
 
+        R0 = P3;
+        call _set_sic_iwr;      /* Set Awake from IDLE */
+
         P0.H = hi(PLL_CTL);
         P0.L = lo(PLL_CTL);
         R0 = W[P0](z);
         BITSET (R0, 3);
-        W[P0] = R0.L;
-
-        R0 = P3;
-        call _set_sic_iwr;
-
+        W[P0] = R0.L;           /* Turn CCLK OFF */
         SSYNC;
         IDLE;
 
         call _test_pll_locked;
 
         R0 = IWR_ENABLE(0);
-        call _set_sic_iwr;
+        call _set_sic_iwr;      /* Set Awake from IDLE PLL */
 
         P0.H = hi(VR_CTL);
         P0.L = lo(VR_CTL);
@@ -352,15 +353,15 @@ ENTRY(_sleep_deeper)
 
         P0.H = hi(PLL_DIV);
         P0.L = lo(PLL_DIV);
-        W[P0]= R6;
+        W[P0]= R6;              /* Restore CCLK and SCLK divider */
 
         P0.H = hi(PLL_CTL);
         P0.L = lo(PLL_CTL);
-        w[p0] = R5;
+        w[p0] = R5;             /* Restore VCO multiplier */
         IDLE;
         call _test_pll_locked;
 
-        call _unset_sdram_srfs;
+        call _unset_dram_srfs;  /* SDRAM Self Refresh Off */
 
         STI R4;
 
@@ -368,25 +369,47 @@ ENTRY(_sleep_deeper)
         ( R7:0, P5:0 ) = [SP++];
         RTS;
 
-ENTRY(_set_sdram_srfs)
-        /*  set the sdram to self refresh mode */
+ENTRY(_set_dram_srfs)
+        /*  set the dram to self refresh mode */
+#if defined(CONFIG_BF54x)
+        P0.H = hi(EBIU_RSTCTL);
+        P0.L = lo(EBIU_RSTCTL);
+        R2 = [P0];
+        R3.H = hi(SRREQ);
+        R3.L = lo(SRREQ);
+#else
         P0.H = hi(EBIU_SDGCTL);
         P0.L = lo(EBIU_SDGCTL);
         R2 = [P0];
         R3.H = hi(SRFS);
         R3.L = lo(SRFS);
+#endif
         R2 = R2|R3;
         [P0] = R2;
         ssync;
+#if defined(CONFIG_BF54x)
+.LSRR_MODE:
+        R2 = [P0];
+        CC = BITTST(R2, 4);
+        if !CC JUMP .LSRR_MODE;
+#endif
         RTS;
 
-ENTRY(_unset_sdram_srfs)
-        /*  set the sdram out of self refresh mode */
+ENTRY(_unset_dram_srfs)
+        /*  set the dram out of self refresh mode */
+#if defined(CONFIG_BF54x)
+        P0.H = hi(EBIU_RSTCTL);
+        P0.L = lo(EBIU_RSTCTL);
+        R2 = [P0];
+        R3.H = hi(SRREQ);
+        R3.L = lo(SRREQ);
+#else
         P0.H = hi(EBIU_SDGCTL);
         P0.L = lo(EBIU_SDGCTL);
         R2 = [P0];
         R3.H = hi(SRFS);
         R3.L = lo(SRFS);
+#endif
         R3 = ~R3;
         R2 = R2&R3;
         [P0] = R2;
@@ -394,8 +417,13 @@ ENTRY(_unset_sdram_srfs)
         RTS;
 
 ENTRY(_set_sic_iwr)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+        P0.H = hi(SIC_IWR0);
+        P0.L = lo(SIC_IWR0);
+#else
         P0.H = hi(SIC_IWR);
         P0.L = lo(SIC_IWR);
+#endif
         [P0] = R0;
         SSYNC;
         RTS;