diff options
Diffstat (limited to 'arch/blackfin/mach-common/cplbmgr.S')
-rw-r--r-- | arch/blackfin/mach-common/cplbmgr.S | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S index e4b47e09cf13..946703ef48ff 100644 --- a/arch/blackfin/mach-common/cplbmgr.S +++ b/arch/blackfin/mach-common/cplbmgr.S | |||
@@ -75,15 +75,15 @@ ENTRY(_cplb_mgr) | |||
75 | * from the configuration table. | 75 | * from the configuration table. |
76 | */ | 76 | */ |
77 | 77 | ||
78 | P4.L = (ICPLB_FAULT_ADDR & 0xFFFF); | 78 | P4.L = LO(ICPLB_FAULT_ADDR); |
79 | P4.H = (ICPLB_FAULT_ADDR >> 16); | 79 | P4.H = HI(ICPLB_FAULT_ADDR); |
80 | 80 | ||
81 | P1 = 16; | 81 | P1 = 16; |
82 | P5.L = _page_size_table; | 82 | P5.L = _page_size_table; |
83 | P5.H = _page_size_table; | 83 | P5.H = _page_size_table; |
84 | 84 | ||
85 | P0.L = (ICPLB_DATA0 & 0xFFFF); | 85 | P0.L = LO(ICPLB_DATA0); |
86 | P0.H = (ICPLB_DATA0 >> 16); | 86 | P0.H = HI(ICPLB_DATA0); |
87 | R4 = [P4]; /* Get faulting address*/ | 87 | R4 = [P4]; /* Get faulting address*/ |
88 | R6 = 64; /* Advance past the fault address, which*/ | 88 | R6 = 64; /* Advance past the fault address, which*/ |
89 | R6 = R6 + R4; /* we'll use if we find a match*/ | 89 | R6 = R6 + R4; /* we'll use if we find a match*/ |
@@ -117,13 +117,13 @@ ENTRY(_cplb_mgr) | |||
117 | I0 = R4; /* Fault address we'll search for*/ | 117 | I0 = R4; /* Fault address we'll search for*/ |
118 | 118 | ||
119 | /* set up pointers */ | 119 | /* set up pointers */ |
120 | P0.L = (ICPLB_DATA0 & 0xFFFF); | 120 | P0.L = LO(ICPLB_DATA0); |
121 | P0.H = (ICPLB_DATA0 >> 16); | 121 | P0.H = HI(ICPLB_DATA0); |
122 | 122 | ||
123 | /* The replacement procedure for ICPLBs */ | 123 | /* The replacement procedure for ICPLBs */ |
124 | 124 | ||
125 | P4.L = (IMEM_CONTROL & 0xFFFF); | 125 | P4.L = LO(IMEM_CONTROL); |
126 | P4.H = (IMEM_CONTROL >> 16); | 126 | P4.H = HI(IMEM_CONTROL); |
127 | 127 | ||
128 | /* disable cplbs */ | 128 | /* disable cplbs */ |
129 | R5 = [P4]; /* Control Register*/ | 129 | R5 = [P4]; /* Control Register*/ |
@@ -243,8 +243,8 @@ ENTRY(_cplb_mgr) | |||
243 | * last entry of the table. | 243 | * last entry of the table. |
244 | */ | 244 | */ |
245 | 245 | ||
246 | P1.L = (ICPLB_DATA15 & 0xFFFF); /* ICPLB_DATA15 */ | 246 | P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */ |
247 | P1.H = (ICPLB_DATA15 >> 16); | 247 | P1.H = HI(ICPLB_DATA15); |
248 | [P1] = R2; | 248 | [P1] = R2; |
249 | [P1-0x100] = R4; | 249 | [P1-0x100] = R4; |
250 | #ifdef CONFIG_CPLB_INFO | 250 | #ifdef CONFIG_CPLB_INFO |
@@ -292,10 +292,10 @@ ENTRY(_cplb_mgr) | |||
292 | * pending writes associated with the CPLB. | 292 | * pending writes associated with the CPLB. |
293 | */ | 293 | */ |
294 | 294 | ||
295 | P4.L = (DCPLB_STATUS & 0xFFFF); | 295 | P4.L = LO(DCPLB_STATUS); |
296 | P4.H = (DCPLB_STATUS >> 16); | 296 | P4.H = HI(DCPLB_STATUS); |
297 | P3.L = (DCPLB_DATA0 & 0xFFFF); | 297 | P3.L = LO(DCPLB_DATA0); |
298 | P3.H = (DCPLB_DATA0 >> 16); | 298 | P3.H = HI(DCPLB_DATA0); |
299 | R5 = [P4]; | 299 | R5 = [P4]; |
300 | 300 | ||
301 | /* A protection violation can be caused by more than just writes | 301 | /* A protection violation can be caused by more than just writes |
@@ -355,11 +355,11 @@ ENTRY(_cplb_mgr) | |||
355 | * config table, that covers the faulting address. | 355 | * config table, that covers the faulting address. |
356 | */ | 356 | */ |
357 | 357 | ||
358 | P1.L = (DCPLB_DATA15 & 0xFFFF); | 358 | P1.L = LO(DCPLB_DATA15); |
359 | P1.H = (DCPLB_DATA15 >> 16); | 359 | P1.H = HI(DCPLB_DATA15); |
360 | 360 | ||
361 | P4.L = (DCPLB_FAULT_ADDR & 0xFFFF); | 361 | P4.L = LO(DCPLB_FAULT_ADDR); |
362 | P4.H = (DCPLB_FAULT_ADDR >> 16); | 362 | P4.H = HI(DCPLB_FAULT_ADDR); |
363 | R4 = [P4]; | 363 | R4 = [P4]; |
364 | I0 = R4; | 364 | I0 = R4; |
365 | 365 | ||
@@ -368,8 +368,8 @@ ENTRY(_cplb_mgr) | |||
368 | R6 = R1; /* Save for later*/ | 368 | R6 = R1; /* Save for later*/ |
369 | 369 | ||
370 | /* Turn off CPLBs while we work.*/ | 370 | /* Turn off CPLBs while we work.*/ |
371 | P4.L = (DMEM_CONTROL & 0xFFFF); | 371 | P4.L = LO(DMEM_CONTROL); |
372 | P4.H = (DMEM_CONTROL >> 16); | 372 | P4.H = HI(DMEM_CONTROL); |
373 | R5 = [P4]; | 373 | R5 = [P4]; |
374 | BITCLR(R5,ENDCPLB_P); | 374 | BITCLR(R5,ENDCPLB_P); |
375 | CLI R0; | 375 | CLI R0; |
@@ -384,8 +384,8 @@ ENTRY(_cplb_mgr) | |||
384 | * are no good. | 384 | * are no good. |
385 | */ | 385 | */ |
386 | 386 | ||
387 | I1.L = (DCPLB_DATA0 & 0xFFFF); | 387 | I1.L = LO(DCPLB_DATA0); |
388 | I1.H = (DCPLB_DATA0 >> 16); | 388 | I1.H = HI(DCPLB_DATA0); |
389 | P1 = 2; | 389 | P1 = 2; |
390 | P2 = 16; | 390 | P2 = 16; |
391 | I2.L = _dcplb_preference; | 391 | I2.L = _dcplb_preference; |
@@ -405,7 +405,7 @@ ENTRY(_cplb_mgr) | |||
405 | P3.L = _page_size_table; /* retrieve end address */ | 405 | P3.L = _page_size_table; /* retrieve end address */ |
406 | P3.H = _page_size_table; /* retrieve end address */ | 406 | P3.H = _page_size_table; /* retrieve end address */ |
407 | R3 = 0x1002; /* 16th - position, 2 bits -length */ | 407 | R3 = 0x1002; /* 16th - position, 2 bits -length */ |
408 | #ifdef ANOMALY_05000209 | 408 | #if ANOMALY_05000209 |
409 | nop; /* Anomaly 05000209 */ | 409 | nop; /* Anomaly 05000209 */ |
410 | #endif | 410 | #endif |
411 | R7 = EXTRACT(R1,R3.l); | 411 | R7 = EXTRACT(R1,R3.l); |
@@ -475,8 +475,8 @@ ENTRY(_cplb_mgr) | |||
475 | * one space closer to the start. | 475 | * one space closer to the start. |
476 | */ | 476 | */ |
477 | 477 | ||
478 | R1.L = (DCPLB_DATA16 & 0xFFFF); /* DCPLB_DATA15 + 4 */ | 478 | R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */ |
479 | R1.H = (DCPLB_DATA16 >> 16); | 479 | R1.H = HI(DCPLB_DATA16); |
480 | R0 = P0; | 480 | R0 = P0; |
481 | 481 | ||
482 | /* If the victim happens to be in DCPLB15, | 482 | /* If the victim happens to be in DCPLB15, |
@@ -549,8 +549,8 @@ ENTRY(_cplb_mgr) | |||
549 | * if necessary. | 549 | * if necessary. |
550 | */ | 550 | */ |
551 | 551 | ||
552 | P1.L = (DCPLB_DATA15 & 0xFFFF); | 552 | P1.L = LO(DCPLB_DATA15); |
553 | P1.H = (DCPLB_DATA15 >> 16); | 553 | P1.H = HI(DCPLB_DATA15); |
554 | 554 | ||
555 | /* If the DCPLB has cache bits set, but caching hasn't | 555 | /* If the DCPLB has cache bits set, but caching hasn't |
556 | * been enabled, then we want to mask off the cache-in-L1 | 556 | * been enabled, then we want to mask off the cache-in-L1 |
@@ -565,7 +565,7 @@ ENTRY(_cplb_mgr) | |||
565 | * cost of first-write exceptions to mark the page as dirty. | 565 | * cost of first-write exceptions to mark the page as dirty. |
566 | */ | 566 | */ |
567 | 567 | ||
568 | #ifdef CONFIG_BLKFIN_WT | 568 | #ifdef CONFIG_BFIN_WT |
569 | BITSET(R6, 14); /* Set WT*/ | 569 | BITSET(R6, 14); /* Set WT*/ |
570 | #endif | 570 | #endif |
571 | 571 | ||