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Diffstat (limited to 'arch/blackfin/mach-common/cacheinit.S')
-rw-r--r-- | arch/blackfin/mach-common/cacheinit.S | 137 |
1 files changed, 137 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S new file mode 100644 index 000000000000..8c17f099e5eb --- /dev/null +++ b/arch/blackfin/mach-common/cacheinit.S | |||
@@ -0,0 +1,137 @@ | |||
1 | /* | ||
2 | * File: arch/blackfin/mach-common/cacheinit.S | ||
3 | * Based on: | ||
4 | * Author: LG Soft India | ||
5 | * | ||
6 | * Created: ? | ||
7 | * Description: cache initialization | ||
8 | * | ||
9 | * Modified: | ||
10 | * Copyright 2004-2006 Analog Devices Inc. | ||
11 | * | ||
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License as published by | ||
16 | * the Free Software Foundation; either version 2 of the License, or | ||
17 | * (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, see the file COPYING, or write | ||
26 | * to the Free Software Foundation, Inc., | ||
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
28 | */ | ||
29 | |||
30 | /* This function sets up the data and instruction cache. The | ||
31 | * tables like icplb table, dcplb table and Page Descriptor table | ||
32 | * are defined in cplbtab.h. You can configure those tables for | ||
33 | * your suitable requirements | ||
34 | */ | ||
35 | |||
36 | #include <linux/linkage.h> | ||
37 | #include <asm/blackfin.h> | ||
38 | |||
39 | .text | ||
40 | |||
41 | #if defined(CONFIG_BLKFIN_CACHE) | ||
42 | ENTRY(_bfin_icache_init) | ||
43 | |||
44 | /* Initialize Instruction CPLBS */ | ||
45 | |||
46 | I0.L = (ICPLB_ADDR0 & 0xFFFF); | ||
47 | I0.H = (ICPLB_ADDR0 >> 16); | ||
48 | |||
49 | I1.L = (ICPLB_DATA0 & 0xFFFF); | ||
50 | I1.H = (ICPLB_DATA0 >> 16); | ||
51 | |||
52 | I2.L = _icplb_table; | ||
53 | I2.H = _icplb_table; | ||
54 | |||
55 | r1 = -1; /* end point comparison */ | ||
56 | r3 = 15; /* max counter */ | ||
57 | |||
58 | /* read entries from table */ | ||
59 | |||
60 | .Lread_iaddr: | ||
61 | R0 = [I2++]; | ||
62 | CC = R0 == R1; | ||
63 | IF CC JUMP .Lidone; | ||
64 | [I0++] = R0; | ||
65 | |||
66 | .Lread_idata: | ||
67 | R2 = [I2++]; | ||
68 | [I1++] = R2; | ||
69 | R3 = R3 + R1; | ||
70 | CC = R3 == R1; | ||
71 | IF !CC JUMP .Lread_iaddr; | ||
72 | |||
73 | .Lidone: | ||
74 | /* Enable Instruction Cache */ | ||
75 | P0.l = (IMEM_CONTROL & 0xFFFF); | ||
76 | P0.h = (IMEM_CONTROL >> 16); | ||
77 | R1 = [P0]; | ||
78 | R0 = (IMC | ENICPLB); | ||
79 | R0 = R0 | R1; | ||
80 | |||
81 | /* Anomaly 05000125 */ | ||
82 | CLI R2; | ||
83 | SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ | ||
84 | .align 8; | ||
85 | [P0] = R0; | ||
86 | SSYNC; | ||
87 | STI R2; | ||
88 | RTS; | ||
89 | #endif | ||
90 | |||
91 | #if defined(CONFIG_BLKFIN_DCACHE) | ||
92 | ENTRY(_bfin_dcache_init) | ||
93 | |||
94 | /* Initialize Data CPLBS */ | ||
95 | |||
96 | I0.L = (DCPLB_ADDR0 & 0xFFFF); | ||
97 | I0.H = (DCPLB_ADDR0 >> 16); | ||
98 | |||
99 | I1.L = (DCPLB_DATA0 & 0xFFFF); | ||
100 | I1.H = (DCPLB_DATA0 >> 16); | ||
101 | |||
102 | I2.L = _dcplb_table; | ||
103 | I2.H = _dcplb_table; | ||
104 | |||
105 | R1 = -1; /* end point comparison */ | ||
106 | R3 = 15; /* max counter */ | ||
107 | |||
108 | /* read entries from table */ | ||
109 | .Lread_daddr: | ||
110 | R0 = [I2++]; | ||
111 | cc = R0 == R1; | ||
112 | IF CC JUMP .Lddone; | ||
113 | [I0++] = R0; | ||
114 | |||
115 | .Lread_ddata: | ||
116 | R2 = [I2++]; | ||
117 | [I1++] = R2; | ||
118 | R3 = R3 + R1; | ||
119 | CC = R3 == R1; | ||
120 | IF !CC JUMP .Lread_daddr; | ||
121 | .Lddone: | ||
122 | P0.L = (DMEM_CONTROL & 0xFFFF); | ||
123 | P0.H = (DMEM_CONTROL >> 16); | ||
124 | R1 = [P0]; | ||
125 | |||
126 | R0 = DMEM_CNTR; | ||
127 | |||
128 | R0 = R0 | R1; | ||
129 | /* Anomaly 05000125 */ | ||
130 | CLI R2; | ||
131 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ | ||
132 | .align 8; | ||
133 | [P0] = R0; | ||
134 | SSYNC; | ||
135 | STI R2; | ||
136 | RTS; | ||
137 | #endif | ||