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-rw-r--r--arch/blackfin/mach-common/cacheinit.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index afa0adfac6c3..22fada0c1cb3 100644
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -39,7 +39,7 @@
39.text 39.text
40 40
41#if ANOMALY_05000125 41#if ANOMALY_05000125
42#if defined(CONFIG_BLKFIN_CACHE) 42#if defined(CONFIG_BFIN_ICACHE)
43ENTRY(_bfin_write_IMEM_CONTROL) 43ENTRY(_bfin_write_IMEM_CONTROL)
44 44
45 /* Enable Instruction Cache */ 45 /* Enable Instruction Cache */
@@ -58,10 +58,10 @@ ENTRY(_bfin_write_IMEM_CONTROL)
58ENDPROC(_bfin_write_IMEM_CONTROL) 58ENDPROC(_bfin_write_IMEM_CONTROL)
59#endif 59#endif
60 60
61#if defined(CONFIG_BLKFIN_DCACHE) 61#if defined(CONFIG_BFIN_DCACHE)
62ENTRY(_bfin_write_DMEM_CONTROL) 62ENTRY(_bfin_write_DMEM_CONTROL)
63 P0.l = (DMEM_CONTROL & 0xFFFF); 63 P0.l = LO(DMEM_CONTROL);
64 P0.h = (DMEM_CONTROL >> 16); 64 P0.h = HI(DMEM_CONTROL);
65 65
66 CLI R1; 66 CLI R1;
67 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ 67 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */