diff options
Diffstat (limited to 'arch/blackfin/mach-common/cache.S')
-rw-r--r-- | arch/blackfin/mach-common/cache.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index bb9446ef66ef..8bd2af1935bd 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S | |||
@@ -70,6 +70,7 @@ ENTRY(_cache_invalidate) | |||
70 | .Lno_dcache_b: | 70 | .Lno_dcache_b: |
71 | R7 = [SP++]; | 71 | R7 = [SP++]; |
72 | RTS; | 72 | RTS; |
73 | ENDPROC(_cache_invalidate) | ||
73 | 74 | ||
74 | /* Invalidate the Entire Instruction cache by | 75 | /* Invalidate the Entire Instruction cache by |
75 | * disabling IMC bit | 76 | * disabling IMC bit |
@@ -106,6 +107,8 @@ ENTRY(_invalidate_entire_icache) | |||
106 | 107 | ||
107 | ( R7:5) = [SP++]; | 108 | ( R7:5) = [SP++]; |
108 | RTS; | 109 | RTS; |
110 | ENDPROC(_invalidate_entire_icache) | ||
111 | ENDPROC(_icache_invalidate) | ||
109 | 112 | ||
110 | /* | 113 | /* |
111 | * blackfin_cache_flush_range(start, end) | 114 | * blackfin_cache_flush_range(start, end) |
@@ -129,6 +132,7 @@ ENTRY(_blackfin_icache_flush_range) | |||
129 | IFLUSH [P0]; | 132 | IFLUSH [P0]; |
130 | SSYNC; | 133 | SSYNC; |
131 | RTS; | 134 | RTS; |
135 | ENDPROC(_blackfin_icache_flush_range) | ||
132 | 136 | ||
133 | /* | 137 | /* |
134 | * blackfin_icache_dcache_flush_range(start, end) | 138 | * blackfin_icache_dcache_flush_range(start, end) |
@@ -155,6 +159,7 @@ ENTRY(_blackfin_icache_dcache_flush_range) | |||
155 | FLUSH [P0]; | 159 | FLUSH [P0]; |
156 | SSYNC; | 160 | SSYNC; |
157 | RTS; | 161 | RTS; |
162 | ENDPROC(_blackfin_icache_dcache_flush_range) | ||
158 | 163 | ||
159 | /* Throw away all D-cached data in specified region without any obligation to | 164 | /* Throw away all D-cached data in specified region without any obligation to |
160 | * write them back. However, we must clean the D-cached entries around the | 165 | * write them back. However, we must clean the D-cached entries around the |
@@ -183,6 +188,7 @@ ENTRY(_blackfin_dcache_invalidate_range) | |||
183 | FLUSHINV[P0]; | 188 | FLUSHINV[P0]; |
184 | SSYNC; | 189 | SSYNC; |
185 | RTS; | 190 | RTS; |
191 | ENDPROC(_blackfin_dcache_invalidate_range) | ||
186 | 192 | ||
187 | /* Invalidate the Entire Data cache by | 193 | /* Invalidate the Entire Data cache by |
188 | * clearing DMC[1:0] bits | 194 | * clearing DMC[1:0] bits |
@@ -221,6 +227,8 @@ ENTRY(_dcache_invalidate) | |||
221 | 227 | ||
222 | ( R7:6) = [SP++]; | 228 | ( R7:6) = [SP++]; |
223 | RTS; | 229 | RTS; |
230 | ENDPROC(_dcache_invalidate) | ||
231 | ENDPROC(_invalidate_entire_dcache) | ||
224 | 232 | ||
225 | ENTRY(_blackfin_dcache_flush_range) | 233 | ENTRY(_blackfin_dcache_flush_range) |
226 | R2 = -L1_CACHE_BYTES; | 234 | R2 = -L1_CACHE_BYTES; |
@@ -241,6 +249,7 @@ ENTRY(_blackfin_dcache_flush_range) | |||
241 | FLUSH[P0]; | 249 | FLUSH[P0]; |
242 | SSYNC; | 250 | SSYNC; |
243 | RTS; | 251 | RTS; |
252 | ENDPROC(_blackfin_dcache_flush_range) | ||
244 | 253 | ||
245 | ENTRY(_blackfin_dflush_page) | 254 | ENTRY(_blackfin_dflush_page) |
246 | P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); | 255 | P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); |
@@ -251,3 +260,4 @@ ENTRY(_blackfin_dflush_page) | |||
251 | .Lfl1: FLUSH [P0++]; | 260 | .Lfl1: FLUSH [P0++]; |
252 | SSYNC; | 261 | SSYNC; |
253 | RTS; | 262 | RTS; |
263 | ENDPROC(_blackfin_dflush_page) | ||