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-rw-r--r--arch/blackfin/mach-bf609/include/mach/anomaly.h54
1 files changed, 44 insertions, 10 deletions
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
index 7a07374308ac..696786e9a531 100644
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -23,11 +23,11 @@
23/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */ 23/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
24#define ANOMALY_16000003 (1) 24#define ANOMALY_16000003 (1)
25/* The EPPI Data Enable (DEN) Signal is Not Functional */ 25/* The EPPI Data Enable (DEN) Signal is Not Functional */
26#define ANOMALY_16000004 (1) 26#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
27/* Using L1 Instruction Cache with Parity Enabled is Unreliable */ 27/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
28#define ANOMALY_16000005 (1) 28#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
29/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */ 29/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
30#define ANOMALY_16000006 (1) 30#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
31/* DDR2 Memory Reads May Fail Intermittently */ 31/* DDR2 Memory Reads May Fail Intermittently */
32#define ANOMALY_16000007 (1) 32#define ANOMALY_16000007 (1)
33/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ 33/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
@@ -49,19 +49,53 @@
49/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 49/* Speculative Fetches Can Cause Undesired External FIFO Operations */
50#define ANOMALY_16000017 (1) 50#define ANOMALY_16000017 (1)
51/* RSI Boot Cleanup Routine Does Not Clear Registers */ 51/* RSI Boot Cleanup Routine Does Not Clear Registers */
52#define ANOMALY_16000018 (1) 52#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
53/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */ 53/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
54#define ANOMALY_16000019 (1) 54#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
55/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */ 55/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
56#define ANOMALY_16000020 (1) 56#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
57/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */ 57/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
58#define ANOMALY_16000021 (1) 58#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
59/* Boot Code Fails to Enable Parity Fault Detection */ 59/* Boot Code Fails to Enable Parity Fault Detection */
60#define ANOMALY_16000022 (1) 60#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
61/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
62#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
63/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
64#define ANOMALY_16000024 (1)
65/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
66#define ANOMALY_16000025 (1)
61/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */ 67/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
62#define ANOMALY_16000027 (1) 68#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
69/* Default SPI Master Boot Mode Setting is Incorrect */
70#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
71/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
72#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
63/* Interrupted Core Reads of MMRs May Cause Data Loss */ 73/* Interrupted Core Reads of MMRs May Cause Data Loss */
64#define ANOMALY_16000030 (1) 74#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
75/* Incorrect Default USB_PLL_OSC.PLLM Value */
76#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
77/* Core Reads of System MMRs May Cause the Core to Hang */
78#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
79/* PPI Data Underflow on First Word Not Reported in Certain Modes */
80#define ANOMALY_16000033 (1)
81/* CNV1 Red Pixel Substitution feature not functional in the PVP */
82#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
83/* IPF0 Output Port Color Separation feature not functional */
84#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
85/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
86#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
87/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
88#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
89/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
90#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
91/* CGU_STAT.PLOCKERR Bit May be Unreliable */
92#define ANOMALY_16000039 (1)
93/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
94#define ANOMALY_16000040 (1)
95/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
96#define ANOMALY_16000041 (1)
97/* Instruction Cache Failure When Parity Is Enabled */
98#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
65 99
66/* Anomalies that don't exist on this proc */ 100/* Anomalies that don't exist on this proc */
67#define ANOMALY_05000158 (0) 101#define ANOMALY_05000158 (0)