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-rw-r--r--arch/blackfin/mach-bf561/head.S4
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h274
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bf561.h223
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h164
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_sir.h125
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h87
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h1579
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h1758
-rw-r--r--arch/blackfin/mach-bf561/include/mach/dma.h35
-rw-r--r--arch/blackfin/mach-bf561/include/mach/irq.h447
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_init.h295
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h78
-rw-r--r--arch/blackfin/mach-bf561/include/mach/portmux.h89
13 files changed, 5156 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index c7a81e34703d..75ea6a905829 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -31,8 +31,8 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach-common/clocks.h> 34#include <asm/clocks.h>
35#include <asm/mach/mem_init.h> 35#include <mach/mem_init.h>
36#endif 36#endif
37 37
38.section .l1.text 38.section .l1.text
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
new file mode 100644
index 000000000000..5c5d7d7d695f
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -0,0 +1,274 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
19#endif
20
21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
22#define ANOMALY_05000074 (1)
23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
25/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
26#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
27/* Testset instructions restricted to 32-bit aligned memory locations */
28#define ANOMALY_05000120 (1)
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1)
31/* Erroneous exception when enabling cache */
32#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
33/* Signbits instruction not functional under certain conditions */
34#define ANOMALY_05000127 (1)
35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
37/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
38#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
39/* Stall in multi-unit DMA operations */
40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
41/* Allowing the SPORT RX FIFO to fill will cause an overflow */
42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
43/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
44#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
47/* DMA and TESTSET conflict when both are accessing external memory */
48#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
49/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
50#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
51/* MDMA may lose the first few words of a descriptor chain */
52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
55/* IMDMA S1/D1 channel may stall */
56#define ANOMALY_05000149 (1)
57/* DMA engine may lose data due to incorrect handshaking */
58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
59/* DMA stalls when all three controllers read data from the same source */
60#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
61/* Execution stall when executing in L2 and doing external accesses */
62#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
63/* Frame Delay in SPORT Multichannel Mode */
64#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
65/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
69/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
70#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
73/* A read from external memory may return a wrong value with data cache enabled */
74#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
75/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
77/* DMEM_CONTROL<12> is not set on Reset */
78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
79/* SPORT transmit data is not gated by external frame sync in certain conditions */
80#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
81/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
82#define ANOMALY_05000166 (1)
83/* Turning Serial Ports on with External Frame Syncs */
84#define ANOMALY_05000167 (1)
85/* SDRAM auto-refresh and subsequent Power Ups */
86#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
87/* DATA CPLB page miss can result in lost write-through cache data writes */
88#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
89/* Boot-ROM code modifies SICA_IWRx wakeup registers */
90#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
91/* DSPID register values incorrect */
92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
93/* DMA vs Core accesses to external memory */
94#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
95/* Cache Fill Buffer Data lost */
96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
97/* Overlapping Sequencer and Memory Stalls */
98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
99/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
104#define ANOMALY_05000180 (1)
105/* Disabling the PPI resets the PPI configuration registers */
106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
107/* IMDMA does not operate to full speed for 600MHz and higher devices */
108#define ANOMALY_05000182 (1)
109/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
111/* PPI TX Mode with 2 External Frame Syncs */
112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
113/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
115/* IMDMA Corrupted Data after a Halt */
116#define ANOMALY_05000187 (1)
117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
119/* False Protection Exceptions */
120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
121/* PPI not functional at core voltage < 1Volt */
122#define ANOMALY_05000190 (1)
123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
125/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
127/* Restarting SPORT in Specific Modes May Cause Data Corruption */
128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
129/* Failing MMR Accesses When Stalled by Preceding Memory Read */
130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
131/* Current DMA Address Shows Wrong Value During Carry Fix */
132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
133/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
135/* Possible Infinite Stall with Specific Dual-DAG Situation */
136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
137/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
139/* Specific sequence that can cause DMA error or DMA stopping */
140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
141/* Recovery from "Brown-Out" Condition */
142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
143/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
144#define ANOMALY_05000208 (1)
145/* Speed Path in Computational Unit Affects Certain Instructions */
146#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
147/* UART TX Interrupt Masked Erroneously */
148#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
149/* NMI Event at Boot Time Results in Unpredictable State */
150#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
151/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
152#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
153/* Incorrect Pulse-Width of UART Start Bit */
154#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
155/* Scratchpad Memory Bank Reads May Return Incorrect Data */
156#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
157/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
159/* UART STB Bit Incorrectly Affects Receiver Setting */
160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
161/* SPORT data transmit lines are incorrectly driven in multichannel mode */
162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
165/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
167/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
169/* TESTSET operation forces stall on the other core */
170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
173/* Exception Not Generated for MMR Accesses in Reserved Region */
174#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
175/* Maximum External Clock Speed for Timers */
176#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
177/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
178#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
179/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
180#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
181/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
182#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
183/* ICPLB_STATUS MMR Register May Be Corrupted */
184#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
185/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
186#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
187/* Stores To Data Cache May Be Lost */
188#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
189/* Hardware Loop Corrupted When Taking an ICPLB Exception */
190#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
191/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
195/* IMDMA destination IRQ status must be read prior to using IMDMA */
196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
197/* IMDMA may corrupt data under certain conditions */
198#define ANOMALY_05000267 (1)
199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
200#define ANOMALY_05000269 (1)
201/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
202#define ANOMALY_05000270 (1)
203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
204#define ANOMALY_05000272 (1)
205/* Data cache write back to external synchronous memory may be lost */
206#define ANOMALY_05000274 (1)
207/* PPI Timing and Sampling Information Updates */
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
211/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
215/* False Hardware Error Exception When ISR Context Is Not Restored */
216#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
217/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
218#define ANOMALY_05000283 (1)
219/* A read will receive incorrect data under certain conditions */
220#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
221/* SPORTs May Receive Bad Data If FIFOs Fill Up */
222#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
223/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
224#define ANOMALY_05000301 (1)
225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
226#define ANOMALY_05000302 (1)
227/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
229/* SCKELOW Bit Does Not Maintain State Through Hibernate */
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
231/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
232#define ANOMALY_05000310 (1)
233/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
234#define ANOMALY_05000312 (1)
235/* PPI Is Level-Sensitive on First Transfer */
236#define ANOMALY_05000313 (1)
237/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
238#define ANOMALY_05000315 (1)
239/* PF2 Output Remains Asserted After SPI Master Boot */
240#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
241/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
242#define ANOMALY_05000323 (1)
243/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
244#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
245/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
246#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
247/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
249/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
251/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
255/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
256#define ANOMALY_05000357 (1)
257/* Conflicting Column Address Widths Causes SDRAM Errors */
258#define ANOMALY_05000362 (1)
259/* UART Break Signal Issues */
260#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
261/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
262#define ANOMALY_05000366 (1)
263/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
264#define ANOMALY_05000371 (1)
265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266#define ANOMALY_05000403 (1)
267
268/* Anomalies that don't exist on this proc */
269#define ANOMALY_05000158 (0)
270#define ANOMALY_05000183 (0)
271#define ANOMALY_05000273 (0)
272#define ANOMALY_05000311 (0)
273
274#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
new file mode 100644
index 000000000000..3ef9e5f36136
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bf561.h
@@ -0,0 +1,223 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/bf561.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF561_H__
31#define __MACH_BF561_H__
32
33#define SUPPORTED_REVID 0x3
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************
53 * Blackfin Cache setup
54 */
55
56
57#define BFIN_ISUBBANKS 4
58#define BFIN_IWAYS 4
59#define BFIN_ILINES 32
60
61#define BFIN_DSUBBANKS 4
62#define BFIN_DWAYS 2
63#define BFIN_DLINES 64
64
65#define WAY0_L 0x1
66#define WAY1_L 0x2
67#define WAY01_L 0x3
68#define WAY2_L 0x4
69#define WAY02_L 0x5
70#define WAY12_L 0x6
71#define WAY012_L 0x7
72
73#define WAY3_L 0x8
74#define WAY03_L 0x9
75#define WAY13_L 0xA
76#define WAY013_L 0xB
77
78#define WAY32_L 0xC
79#define WAY320_L 0xD
80#define WAY321_L 0xE
81#define WAYALL_L 0xF
82
83#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
84
85/* IAR0 BIT FIELDS */
86#define PLL_WAKEUP_BIT 0xFFFFFFFF
87#define DMA1_ERROR_BIT 0xFFFFFF0F
88#define DMA2_ERROR_BIT 0xFFFFF0FF
89#define IMDMA_ERROR_BIT 0xFFFF0FFF
90#define PPI1_ERROR_BIT 0xFFF0FFFF
91#define PPI2_ERROR_BIT 0xFF0FFFFF
92#define SPORT0_ERROR_BIT 0xF0FFFFFF
93#define SPORT1_ERROR_BIT 0x0FFFFFFF
94/* IAR1 BIT FIELDS */
95#define SPI_ERROR_BIT 0xFFFFFFFF
96#define UART_ERROR_BIT 0xFFFFFF0F
97#define RESERVED_ERROR_BIT 0xFFFFF0FF
98#define DMA1_0_BIT 0xFFFF0FFF
99#define DMA1_1_BIT 0xFFF0FFFF
100#define DMA1_2_BIT 0xFF0FFFFF
101#define DMA1_3_BIT 0xF0FFFFFF
102#define DMA1_4_BIT 0x0FFFFFFF
103/* IAR2 BIT FIELDS */
104#define DMA1_5_BIT 0xFFFFFFFF
105#define DMA1_6_BIT 0xFFFFFF0F
106#define DMA1_7_BIT 0xFFFFF0FF
107#define DMA1_8_BIT 0xFFFF0FFF
108#define DMA1_9_BIT 0xFFF0FFFF
109#define DMA1_10_BIT 0xFF0FFFFF
110#define DMA1_11_BIT 0xF0FFFFFF
111#define DMA2_0_BIT 0x0FFFFFFF
112/* IAR3 BIT FIELDS */
113#define DMA2_1_BIT 0xFFFFFFFF
114#define DMA2_2_BIT 0xFFFFFF0F
115#define DMA2_3_BIT 0xFFFFF0FF
116#define DMA2_4_BIT 0xFFFF0FFF
117#define DMA2_5_BIT 0xFFF0FFFF
118#define DMA2_6_BIT 0xFF0FFFFF
119#define DMA2_7_BIT 0xF0FFFFFF
120#define DMA2_8_BIT 0x0FFFFFFF
121/* IAR4 BIT FIELDS */
122#define DMA2_9_BIT 0xFFFFFFFF
123#define DMA2_10_BIT 0xFFFFFF0F
124#define DMA2_11_BIT 0xFFFFF0FF
125#define TIMER0_BIT 0xFFFF0FFF
126#define TIMER1_BIT 0xFFF0FFFF
127#define TIMER2_BIT 0xFF0FFFFF
128#define TIMER3_BIT 0xF0FFFFFF
129#define TIMER4_BIT 0x0FFFFFFF
130/* IAR5 BIT FIELDS */
131#define TIMER5_BIT 0xFFFFFFFF
132#define TIMER6_BIT 0xFFFFFF0F
133#define TIMER7_BIT 0xFFFFF0FF
134#define TIMER8_BIT 0xFFFF0FFF
135#define TIMER9_BIT 0xFFF0FFFF
136#define TIMER10_BIT 0xFF0FFFFF
137#define TIMER11_BIT 0xF0FFFFFF
138#define PROG0_INTA_BIT 0x0FFFFFFF
139/* IAR6 BIT FIELDS */
140#define PROG0_INTB_BIT 0xFFFFFFFF
141#define PROG1_INTA_BIT 0xFFFFFF0F
142#define PROG1_INTB_BIT 0xFFFFF0FF
143#define PROG2_INTA_BIT 0xFFFF0FFF
144#define PROG2_INTB_BIT 0xFFF0FFFF
145#define DMA1_WRRD0_BIT 0xFF0FFFFF
146#define DMA1_WRRD1_BIT 0xF0FFFFFF
147#define DMA2_WRRD0_BIT 0x0FFFFFFF
148/* IAR7 BIT FIELDS */
149#define DMA2_WRRD1_BIT 0xFFFFFFFF
150#define IMDMA_WRRD0_BIT 0xFFFFFF0F
151#define IMDMA_WRRD1_BIT 0xFFFFF0FF
152#define WATCH_BIT 0xFFFF0FFF
153#define RESERVED_1_BIT 0xFFF0FFFF
154#define RESERVED_2_BIT 0xFF0FFFFF
155#define SUPPLE_0_BIT 0xF0FFFFFF
156#define SUPPLE_1_BIT 0x0FFFFFFF
157
158/* Miscellaneous Values */
159
160/****************************** EBIU Settings ********************************/
161#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
162#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
163
164#if defined(CONFIG_C_AMBEN_ALL)
165#define V_AMBEN AMBEN_ALL
166#elif defined(CONFIG_C_AMBEN)
167#define V_AMBEN 0x0
168#elif defined(CONFIG_C_AMBEN_B0)
169#define V_AMBEN AMBEN_B0
170#elif defined(CONFIG_C_AMBEN_B0_B1)
171#define V_AMBEN AMBEN_B0_B1
172#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
173#define V_AMBEN AMBEN_B0_B1_B2
174#endif
175
176#ifdef CONFIG_C_AMCKEN
177#define V_AMCKEN AMCKEN
178#else
179#define V_AMCKEN 0x0
180#endif
181
182#ifdef CONFIG_C_B0PEN
183#define V_B0PEN 0x10
184#else
185#define V_B0PEN 0x00
186#endif
187
188#ifdef CONFIG_C_B1PEN
189#define V_B1PEN 0x20
190#else
191#define V_B1PEN 0x00
192#endif
193
194#ifdef CONFIG_C_B2PEN
195#define V_B2PEN 0x40
196#else
197#define V_B2PEN 0x00
198#endif
199
200#ifdef CONFIG_C_B3PEN
201#define V_B3PEN 0x80
202#else
203#define V_B3PEN 0x00
204#endif
205
206#ifdef CONFIG_C_CDPRIO
207#define V_CDPRIO 0x100
208#else
209#define V_CDPRIO 0x0
210#endif
211
212#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
213
214#ifdef CONFIG_BF561
215#define CPU "BF561"
216#define CPUID 0x027bb000
217#endif
218#ifndef CPU
219#define CPU "UNKNOWN"
220#define CPUID 0x0
221#endif
222
223#endif /* __MACH_BF561_H__ */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..8aa02780e642
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,164 @@
1/*
2 * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61
62#ifdef CONFIG_BFIN_UART0_CTSRTS
63# define CONFIG_SERIAL_BFIN_CTSRTS
64# ifndef CONFIG_UART0_CTS_PIN
65# define CONFIG_UART0_CTS_PIN -1
66# endif
67# ifndef CONFIG_UART0_RTS_PIN
68# define CONFIG_UART0_RTS_PIN -1
69# endif
70#endif
71
72struct bfin_serial_port {
73 struct uart_port port;
74 unsigned int old_status;
75 unsigned int lsr;
76#ifdef CONFIG_SERIAL_BFIN_DMA
77 int tx_done;
78 int tx_count;
79 struct circ_buf rx_dma_buf;
80 struct timer_list rx_dma_timer;
81 int rx_dma_nrows;
82 unsigned int tx_dma_channel;
83 unsigned int rx_dma_channel;
84 struct work_struct tx_dma_workqueue;
85#else
86# if ANOMALY_05000230
87 unsigned int anomaly_threshold;
88# endif
89#endif
90#ifdef CONFIG_SERIAL_BFIN_CTSRTS
91 struct timer_list cts_timer;
92 int cts_pin;
93 int rts_pin;
94#endif
95};
96
97/* The hardware clears the LSR bits upon read, so we need to cache
98 * some of the more fun bits in software so they don't get lost
99 * when checking the LSR in other code paths (TX).
100 */
101static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
102{
103 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
104 uart->lsr |= (lsr & (BI|FE|PE|OE));
105 return lsr | uart->lsr;
106}
107
108static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
109{
110 uart->lsr = 0;
111 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
112}
113
114struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
115struct bfin_serial_res {
116 unsigned long uart_base_addr;
117 int uart_irq;
118#ifdef CONFIG_SERIAL_BFIN_DMA
119 unsigned int uart_tx_dma_channel;
120 unsigned int uart_rx_dma_channel;
121#endif
122#ifdef CONFIG_SERIAL_BFIN_CTSRTS
123 int uart_cts_pin;
124 int uart_rts_pin;
125#endif
126};
127
128struct bfin_serial_res bfin_serial_resource[] = {
129 {
130 0xFFC00400,
131 IRQ_UART_RX,
132#ifdef CONFIG_SERIAL_BFIN_DMA
133 CH_UART_TX,
134 CH_UART_RX,
135#endif
136#ifdef CONFIG_BFIN_UART0_CTSRTS
137 CONFIG_UART0_CTS_PIN,
138 CONFIG_UART0_RTS_PIN,
139#endif
140 }
141};
142
143#define DRIVER_NAME "bfin-uart"
144
145int nr_ports = BFIN_UART_NR_PORTS;
146static void bfin_serial_hw_init(struct bfin_serial_port *uart)
147{
148
149#ifdef CONFIG_SERIAL_BFIN_UART0
150 peripheral_request(P_UART0_TX, DRIVER_NAME);
151 peripheral_request(P_UART0_RX, DRIVER_NAME);
152#endif
153
154#ifdef CONFIG_SERIAL_BFIN_CTSRTS
155 if (uart->cts_pin >= 0) {
156 gpio_request(uart->cts_pin, DRIVER_NAME);
157 gpio_direction_input(uart->cts_pin);
158 }
159 if (uart->rts_pin >= 0) {
160 gpio_request(uart->rts_pin, DRIVER_NAME);
161 gpio_direction_input(uart->rts_pin, 0);
162 }
163#endif
164}
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h b/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..9bb87e9e2e9b
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
@@ -0,0 +1,125 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static int bfin_sir_hw_init(void)
114{
115 int ret = -ENODEV;
116#ifdef CONFIG_BFIN_SIR0
117 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
118 if (ret)
119 return ret;
120 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
121 if (ret)
122 return ret;
123#endif
124 return ret;
125}
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
new file mode 100644
index 000000000000..0ea8666e6764
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -0,0 +1,87 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MACH_BLACKFIN_H_
32#define _MACH_BLACKFIN_H_
33
34#define BF561_FAMILY
35
36#include "bf561.h"
37#include "mem_map.h"
38#include "defBF561.h"
39#include "anomaly.h"
40
41#if !defined(__ASSEMBLY__)
42#include "cdefBF561.h"
43#endif
44
45#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
46#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
47#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
48#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
51
52#define SIC_IWR0 SICA_IWR0
53#define SIC_IWR1 SICA_IWR1
54#define SIC_IAR0 SICA_IAR0
55#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
56#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
57#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
58#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
59
60#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
61#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
62#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
63#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
64#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
65#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
66
67#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
68#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
71
72#define BFIN_UART_NR_PORTS 1
73
74#define OFFSET_THR 0x00 /* Transmit Holding register */
75#define OFFSET_RBR 0x00 /* Receive Buffer register */
76#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
77#define OFFSET_IER 0x04 /* Interrupt Enable Register */
78#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
79#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
80#define OFFSET_LCR 0x0C /* Line Control Register */
81#define OFFSET_MCR 0x10 /* Modem Control Register */
82#define OFFSET_LSR 0x14 /* Line Status Register */
83#define OFFSET_MSR 0x18 /* Modem Status Register */
84#define OFFSET_SCR 0x1C /* SCR Scratch Register */
85#define OFFSET_GCTL 0x24 /* Global Control Register */
86
87#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
new file mode 100644
index 000000000000..c14d63402e70
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -0,0 +1,1579 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/cdefBF561.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF561_H
32#define _CDEF_BF561_H
33
34#include <asm/blackfin.h>
35
36/* include all Core registers and bit definitions */
37#include "defBF561.h"
38
39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h>
41
42#include <asm/system.h>
43
44/*********************************************************************************** */
45/* System MMR Register Map */
46/*********************************************************************************** */
47
48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
50/* Writing to PLL_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_PLL_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1;
54
55 if (val == bfin_read_PLL_CTL())
56 return;
57
58 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1);
62 /* Only allow PPL Wakeup) */
63 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
64 bfin_write32(SICA_IWR1, 0);
65
66 bfin_write16(PLL_CTL, val);
67 SSYNC();
68 asm("IDLE;");
69
70 bfin_write32(SICA_IWR0, iwr0);
71 bfin_write32(SICA_IWR1, iwr1);
72 local_irq_restore(flags);
73}
74#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
75#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
76#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
77/* Writing to VR_CTL initiates a PLL relock sequence. */
78static __inline__ void bfin_write_VR_CTL(unsigned int val)
79{
80 unsigned long flags, iwr0, iwr1;
81
82 if (val == bfin_read_VR_CTL())
83 return;
84
85 local_irq_save(flags);
86 /* Enable the PLL Wakeup bit in SIC IWR */
87 iwr0 = bfin_read32(SICA_IWR0);
88 iwr1 = bfin_read32(SICA_IWR1);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
91 bfin_write32(SICA_IWR1, 0);
92
93 bfin_write16(VR_CTL, val);
94 SSYNC();
95 asm("IDLE;");
96
97 bfin_write32(SICA_IWR0, iwr0);
98 bfin_write32(SICA_IWR1, iwr1);
99 local_irq_restore(flags);
100}
101#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
102#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
103#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
104#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
105#define bfin_read_CHIPID() bfin_read32(CHIPID)
106
107/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
108#define bfin_read_SWRST() bfin_read_SICA_SWRST()
109#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
110#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
111#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
112
113/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
114#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
115#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)
116#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
117#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val)
118#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
119#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val)
120#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK)
121#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val)
122#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)
123#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val)
124#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)
125#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val)
126#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)
127#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val)
128#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)
129#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val)
130#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)
131#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val)
132#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)
133#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val)
134#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)
135#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val)
136#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)
137#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val)
138#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)
139#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val)
140#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
141#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val)
142#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)
143#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val)
144#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)
145#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val)
146#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)
147#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val)
148#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
149#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
150
151/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
152#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
153#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
154#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
155#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
156#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
157#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
158#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
159#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
160#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
161#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
162#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
163#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
164#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
165#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
166#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
167#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
168#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
169#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
170#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
171#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
172#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
173#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
174#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
175#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
176#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
177#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
178#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
179#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
180#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
181#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
182#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
183#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
184#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
185#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
186/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
187#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
188#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
189#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
190#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
191#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
192#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
193
194/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
195#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
196#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
197#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
198#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
199#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
200#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
201
202/* UART Controller (0xFFC00400 - 0xFFC004FF) */
203#define bfin_read_UART_THR() bfin_read16(UART_THR)
204#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
205#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
206#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
207#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
208#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
209#define bfin_read_UART_IER() bfin_read16(UART_IER)
210#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
211#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
212#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
213#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
214#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
215#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
216#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
217#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
218#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
219#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
220#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
221#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
222#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
223#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
224#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
225#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
226#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
227
228/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
229#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
230#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
231#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
232#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
233#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
234#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
235#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
236#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
237#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
238#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
239#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
240#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
241#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
242#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
243
244/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
245#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
246#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
247#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
248#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
249#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
250#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
251#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
252#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
253#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
254#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
255#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
256#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
257#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
258#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
259#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
260#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
261#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
262#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
263#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
264#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
265#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
266#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
267#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
268#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
269#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
270#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
271#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
272#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
273#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
274#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
275#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
276#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
277#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
278#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
279#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
280#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
281#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
282#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
283#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
284#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
285#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
286#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
287#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
288#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
289#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
290#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
291#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
292#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
293#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
294#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
295#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
296#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
297#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
298#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
299#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
300#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
301#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
302#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
303#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
304#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
305#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
306#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
307#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
308#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
309
310/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
311#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE)
312#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
313#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE)
314#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
315#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
316#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
317#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
318#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
319#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
320#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
321#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
322#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
323#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
324#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
325#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
326#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
327#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
328#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
329#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
330#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
331#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
332#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
333#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
334#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
335#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
336#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
337#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
338#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
339#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
340#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
341#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
342#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
343#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
344#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
345#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
346#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
347#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
348#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
349#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE)
350#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
351#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE)
352#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
353#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
354#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
355
356/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
357#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
358#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
359#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
360#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
361#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
362#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
363#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
364#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
365#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
366#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
367#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
368#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
369#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
370#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
371#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
372#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
373#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
374#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
375#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
376#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
377#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
378#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
379#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
380#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
381#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
382#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
383#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
384#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
385#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
386#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
387#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
388#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
389#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
390#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
391/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
392#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
393#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
394#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
395#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
396#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
397#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
398#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
399#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
400#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
401#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
402#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
403#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
404#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
405#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
406#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
407#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
408#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
409#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
410#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
411#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
412#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
413#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
414#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
415#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
416#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
417#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
418#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
419#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
420#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
421#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
422#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
423#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
424#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
425#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
426/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
427#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
428#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
429#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
430#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
431#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
432#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
433#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
434#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
435#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
436#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
437#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
438#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
439#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
440#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
441#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
442#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
443#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
444#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
445#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
446#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
447#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
448#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
449#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
450#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
451#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
452#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
453#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
454#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
455#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
456#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
457#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
458#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
459#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
460#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
461/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
462#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
463#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
464#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
465#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
466#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
467#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
468#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
469#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
470#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
471#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
472#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
473#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
474#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
475#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
476#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
477#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
478#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
479#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
480#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
481#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
482#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
483#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
484#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
485#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
486#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
487#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
488#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
489#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
490#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
491#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
492#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
493#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
494#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
495#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
496#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
497#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
498#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
499#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
500#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
501#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
502#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
503#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
504#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
505#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
506#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
507#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
508#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
509#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
510#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
511#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
512#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
513#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
514/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
515#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
516#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
517#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
518#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
519#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
520#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
521#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
522#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
523#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
524#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
525#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
526#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
527#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
528#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
529#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
530#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
531#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
532#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
533#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
534#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
535#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
536#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
537#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
538#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
539#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
540#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
541#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
542#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
543#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
544#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
545#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
546#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
547#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
548#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
549#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
550#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
551#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
552#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
553#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
554#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
555#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
556#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
557#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
558#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
559#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
560#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
561#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
562#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
563#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
564#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
565#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
566#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
567/* Asynchronous Memory Controller - External Bus Interface Unit */
568#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
569#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
570#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
571#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
572#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
573#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
574/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
575#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
576#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
577#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
578#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
579#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
580#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
581#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
582#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
583/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
584#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
585#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
586#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
587#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
588#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
589#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
590#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
591#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
592#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
593#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
594#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
595/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
596#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
597#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
598#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
599#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
600#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
601#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
602#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
603#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
604#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
605#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
606#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
607/*DMA traffic control registers */
608#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
609#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val)
610#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
611#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val)
612#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER)
613#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val)
614#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT)
615#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val)
616/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
617#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
618#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
619#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
620#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
621#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR)
622#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
623#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
624#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
625#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
626#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
627#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
628#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
629#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
630#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
631#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR)
632#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
633#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR)
634#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
635#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
636#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
637#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
638#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
639#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
640#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
641#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
642#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
643#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
644#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
645#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR)
646#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
647#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR)
648#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
649#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
650#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
651#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
652#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
653#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
654#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
655#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
656#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
657#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR)
658#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
659#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR)
660#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
661#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
662#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
663#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
664#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
665#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
666#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
667#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
668#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
669#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
670#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
671#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR)
672#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
673#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR)
674#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
675#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
676#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
677#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
678#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
679#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
680#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
681#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
682#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
683#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR)
684#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
685#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR)
686#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
687#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
688#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
689#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
690#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
691#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
692#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
693#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
694#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
695#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
696#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
697#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR)
698#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
699#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR)
700#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
701#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
702#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
703#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
704#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
705#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
706#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
707#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
708#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
709#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR)
710#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
711#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR)
712#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
713#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
714#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
715#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
716#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
717#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
718#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
719#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
720#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
721#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
722#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
723#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR)
724#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
725#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR)
726#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
727#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
728#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
729#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
730#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
731#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
732#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
733#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
734#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
735#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR)
736#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
737#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR)
738#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
739#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
740#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
741#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
742#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
743#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
744#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
745#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
746#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
747#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
748#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
749#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR)
750#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
751#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR)
752#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
753#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
754#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
755#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
756#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
757#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
758#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
759#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
760#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
761#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR)
762#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
763#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR)
764#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
765#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
766#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
767#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
768#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
769#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
770#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
771#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
772#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
773#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
774#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
775#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR)
776#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
777#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR)
778#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
779#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
780#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
781#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
782#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
783#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
784#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
785#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
786#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
787#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR)
788#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
789#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR)
790#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
791#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
792#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
793#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
794#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
795#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
796#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
797#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
798#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
799#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
800#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
801#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR)
802#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
803#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR)
804#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
805#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
806#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
807#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
808#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
809#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
810#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
811#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
812#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
813#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR)
814#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
815#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR)
816#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
817#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
818#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
819#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
820#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
821#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
822#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
823#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
824#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
825#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
826#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
827#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR)
828#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
829#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR)
830#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
831#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
832#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
833#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
834#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
835#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
836#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
837#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
838#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
839#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR)
840#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
841#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR)
842#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
843#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
844#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
845#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
846#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
847#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
848#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
849#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
850#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
851#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
852#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
853#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR)
854#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
855#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR)
856#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
857#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
858#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
859#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
860#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
861#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
862#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
863#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
864#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
865#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR)
866#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
867#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR)
868#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
869#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
870#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
871#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
872#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
873#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
874#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
875#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
876#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
877#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
878#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
879#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR)
880#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
881#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR)
882#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
883#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
884#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
885#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
886#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
887#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
888#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
889#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
890#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
891#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR)
892#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
893#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR)
894#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
895#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
896#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
897#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
898#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
899#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
900#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
901#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
902#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
903#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
904#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
905#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR)
906#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
907#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR)
908#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
909#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
910#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
911#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
912#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
913#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
914#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
915#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
916#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
917#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR)
918#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
919#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR)
920#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
921#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
922#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
923#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
924#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
925#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
926#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
927#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
928#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
929/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
930#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
931#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val)
932#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
933#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
934#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR)
935#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val)
936#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
937#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val)
938#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
939#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val)
940#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
941#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val)
942#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
943#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val)
944#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR)
945#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
946#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR)
947#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val)
948#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
949#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
950#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
951#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
952#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
953#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val)
954#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
955#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
956#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
957#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val)
958#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
959#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
960#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR)
961#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val)
962#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
963#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val)
964#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
965#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val)
966#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
967#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val)
968#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
969#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val)
970#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR)
971#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
972#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR)
973#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val)
974#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
975#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
976#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
977#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
978#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
979#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val)
980#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
981#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
982#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
983#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val)
984#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
985#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
986#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR)
987#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val)
988#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
989#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val)
990#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
991#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val)
992#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
993#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val)
994#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
995#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val)
996#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR)
997#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
998#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR)
999#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val)
1000#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
1001#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
1002#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
1003#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
1004#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
1005#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val)
1006#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
1007#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
1008#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
1009#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val)
1010#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
1011#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
1012#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR)
1013#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val)
1014#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
1015#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val)
1016#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
1017#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val)
1018#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
1019#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val)
1020#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
1021#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val)
1022#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR)
1023#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
1024#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR)
1025#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val)
1026#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
1027#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
1028#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
1029#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
1030#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
1031#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val)
1032#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
1033#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
1034/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
1035#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
1036#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
1037#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR)
1038#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
1039#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR)
1040#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
1041#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
1042#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
1043#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
1044#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
1045#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
1046#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
1047#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
1048#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
1049#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR)
1050#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
1051#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR)
1052#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
1053#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
1054#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
1055#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
1056#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
1057#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
1058#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
1059#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
1060#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
1061#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
1062#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
1063#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR)
1064#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
1065#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR)
1066#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
1067#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
1068#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
1069#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
1070#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
1071#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
1072#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
1073#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
1074#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
1075#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR)
1076#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
1077#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR)
1078#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
1079#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
1080#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
1081#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
1082#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
1083#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
1084#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
1085#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
1086#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
1087#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
1088#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
1089#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR)
1090#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
1091#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR)
1092#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
1093#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
1094#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
1095#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
1096#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
1097#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
1098#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
1099#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
1100#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
1101#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR)
1102#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
1103#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR)
1104#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
1105#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
1106#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
1107#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
1108#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
1109#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
1110#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
1111#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
1112#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
1113#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
1114#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
1115#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR)
1116#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
1117#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR)
1118#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
1119#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
1120#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
1121#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
1122#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
1123#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
1124#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
1125#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
1126#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
1127#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR)
1128#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
1129#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR)
1130#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
1131#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
1132#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
1133#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
1134#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
1135#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
1136#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
1137#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
1138#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
1139#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
1140#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
1141#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR)
1142#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
1143#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR)
1144#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
1145#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
1146#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
1147#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
1148#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
1149#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
1150#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
1151#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
1152#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
1153#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR)
1154#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
1155#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR)
1156#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
1157#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
1158#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
1159#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
1160#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
1161#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
1162#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
1163#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
1164#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
1165#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
1166#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
1167#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR)
1168#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
1169#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR)
1170#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
1171#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
1172#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
1173#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
1174#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
1175#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
1176#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
1177#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
1178#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
1179#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR)
1180#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
1181#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR)
1182#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
1183#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
1184#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
1185#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
1186#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
1187#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
1188#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
1189#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
1190#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
1191#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
1192#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
1193#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR)
1194#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
1195#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR)
1196#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
1197#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
1198#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
1199#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
1200#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
1201#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
1202#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
1203#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
1204#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
1205#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR)
1206#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
1207#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR)
1208#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
1209#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
1210#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
1211#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
1212#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
1213#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
1214#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
1215#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
1216#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
1217#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
1218#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
1219#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR)
1220#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
1221#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR)
1222#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
1223#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
1224#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
1225#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
1226#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
1227#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
1228#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
1229#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
1230#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
1231#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR)
1232#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
1233#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR)
1234#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
1235#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
1236#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
1237#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
1238#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
1239#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
1240#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
1241#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
1242#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
1243#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
1244#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
1245#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR)
1246#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
1247#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR)
1248#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
1249#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
1250#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
1251#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
1252#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
1253#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
1254#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
1255#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
1256#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
1257#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR)
1258#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
1259#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR)
1260#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
1261#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
1262#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
1263#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
1264#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
1265#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
1266#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
1267#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
1268#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
1269#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
1270#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
1271#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR)
1272#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
1273#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR)
1274#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
1275#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
1276#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
1277#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
1278#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
1279#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
1280#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
1281#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
1282#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
1283#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR)
1284#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
1285#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR)
1286#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
1287#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
1288#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
1289#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
1290#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
1291#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
1292#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
1293#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
1294#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
1295#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
1296#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
1297#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR)
1298#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
1299#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR)
1300#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
1301#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
1302#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
1303#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
1304#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
1305#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
1306#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
1307#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
1308#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
1309#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR)
1310#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
1311#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR)
1312#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
1313#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
1314#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
1315#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
1316#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
1317#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
1318#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
1319#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
1320#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
1321#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
1322#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
1323#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR)
1324#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
1325#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR)
1326#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
1327#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
1328#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
1329#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
1330#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
1331#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
1332#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
1333#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
1334#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
1335#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR)
1336#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
1337#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR)
1338#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
1339#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
1340#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
1341#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
1342#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
1343#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
1344#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
1345#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
1346#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
1347/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
1348#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG)
1349#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val)
1350#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
1351#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
1352#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR)
1353#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val)
1354#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT)
1355#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val)
1356#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT)
1357#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val)
1358#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY)
1359#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val)
1360#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY)
1361#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val)
1362#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR)
1363#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
1364#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR)
1365#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val)
1366#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
1367#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
1368#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
1369#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
1370#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
1371#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val)
1372#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
1373#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
1374#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG)
1375#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val)
1376#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
1377#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
1378#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR)
1379#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val)
1380#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT)
1381#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val)
1382#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT)
1383#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val)
1384#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY)
1385#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val)
1386#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY)
1387#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val)
1388#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR)
1389#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
1390#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR)
1391#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val)
1392#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
1393#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
1394#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
1395#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
1396#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
1397#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val)
1398#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
1399#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
1400#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG)
1401#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val)
1402#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
1403#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
1404#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR)
1405#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val)
1406#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT)
1407#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val)
1408#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT)
1409#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val)
1410#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY)
1411#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val)
1412#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY)
1413#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val)
1414#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR)
1415#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
1416#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR)
1417#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val)
1418#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
1419#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
1420#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
1421#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
1422#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
1423#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val)
1424#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
1425#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
1426#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG)
1427#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val)
1428#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
1429#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
1430#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR)
1431#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val)
1432#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT)
1433#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val)
1434#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT)
1435#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val)
1436#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY)
1437#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val)
1438#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY)
1439#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val)
1440#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR)
1441#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
1442#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR)
1443#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val)
1444#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
1445#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
1446#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
1447#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
1448#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
1449#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val)
1450#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
1451#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
1452/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
1453#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
1454#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
1455#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
1456#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
1457#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR)
1458#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
1459#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
1460#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
1461#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
1462#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
1463#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
1464#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
1465#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
1466#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
1467#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR)
1468#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
1469#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR)
1470#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
1471#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
1472#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
1473#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
1474#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
1475#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
1476#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
1477#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
1478#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
1479#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
1480#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
1481#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR)
1482#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
1483#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
1484#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
1485#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
1486#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
1487#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
1488#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
1489#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
1490#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
1491#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR)
1492#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
1493#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR)
1494#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
1495#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
1496#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
1497#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
1498#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
1499#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
1500#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
1501#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
1502#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
1503#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
1504#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
1505#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR)
1506#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
1507#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
1508#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
1509#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
1510#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
1511#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
1512#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
1513#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
1514#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
1515#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR)
1516#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
1517#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR)
1518#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
1519#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
1520#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
1521#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
1522#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
1523#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
1524#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
1525#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
1526#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
1527#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
1528#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
1529#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR)
1530#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
1531#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
1532#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
1533#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
1534#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
1535#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
1536#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
1537#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
1538#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
1539#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR)
1540#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
1541#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR)
1542#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
1543#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
1544#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
1545#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
1546#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
1547#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
1548#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
1549
1550#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG()
1551#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
1552#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS()
1553#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
1554#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY()
1555#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
1556#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY()
1557#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
1558#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT()
1559#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
1560#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT()
1561#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
1562#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR()
1563#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
1564#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG()
1565#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
1566#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS()
1567#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
1568#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY()
1569#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
1570#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY()
1571#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
1572#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT()
1573#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
1574#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT()
1575#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
1576#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1577#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1578
1579#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
new file mode 100644
index 000000000000..4eca2026bb92
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -0,0 +1,1758 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf561/defBF561.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _DEF_BF561_H
33#define _DEF_BF561_H
34/*
35#if !defined(__ADSPBF561__)
36#warning defBF561.h should only be included for BF561 chip.
37#endif
38*/
39/* include all Core registers and bit definitions */
40#include <asm/def_LPBlackfin.h>
41
42/*********************************************************************************** */
43/* System MMR Register Map */
44/*********************************************************************************** */
45
46/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
47
48#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
49#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
50#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
51#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
52#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
53#define CHIPID 0xFFC00014 /* Chip ID Register */
54
55/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
56#define SWRST SICA_SWRST
57#define SYSCR SICA_SYSCR
58#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
59#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
60#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
61#define RESET_SOFTWARE (SWRST_OCCURRED)
62
63/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
64#define SICA_SWRST 0xFFC00100 /* Software Reset register */
65#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */
66#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
67#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */
68#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
69#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
70#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
71#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
72#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
73#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
74#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
75#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
76#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
77#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
78#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
79#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
80#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
81#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
82
83/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
84#define SICB_SWRST 0xFFC01100 /* reserved */
85#define SICB_SYSCR 0xFFC01104 /* reserved */
86#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
87#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
88#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
89#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
90#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
91#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
92#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
93#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
94#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
95#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
96#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
97#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
98#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
99#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
100#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
101
102/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
103#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
104#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
105#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
106
107/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
108#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
109#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
110#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
111
112/* UART Controller (0xFFC00400 - 0xFFC004FF) */
113
114/*
115 * Because include/linux/serial_reg.h have defined UART_*,
116 * So we define blackfin uart regs to BFIN_UART0_*.
117 */
118#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
119#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
120#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
121#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
122#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
123#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
124#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
125#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
126#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
127#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
128#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
129#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
130
131/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
132#define SPI0_REGBASE 0xFFC00500
133#define SPI_CTL 0xFFC00500 /* SPI Control Register */
134#define SPI_FLG 0xFFC00504 /* SPI Flag register */
135#define SPI_STAT 0xFFC00508 /* SPI Status register */
136#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
137#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
138#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
139#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
140
141/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
142#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
143#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
144#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
145#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
146
147#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
148#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
149#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
150#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
151
152#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
153#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
154#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
155#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
156
157#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
158#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
159#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
160#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
161
162#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
163#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
164#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
165#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
166
167#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
168#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
169#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
170#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
171
172#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
173#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
174#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
175#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
176
177#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
178#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
179#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
180#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
181
182#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
183#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
184#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
185
186/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
187#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
188#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
189#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
190#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
191
192#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
193#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
194#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
195#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
196
197#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
198#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
199#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
200#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
201
202#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
203#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
204#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
205#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
206
207#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
208#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
209#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
210
211/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
212#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
213#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
214#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
215#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
216#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
217#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
218#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
219#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
220#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
221#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
222#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
223#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
224#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
225#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
226#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
227#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
228#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
229
230/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
231#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
232#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
233#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
234#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
235#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
236#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
237#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
238#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
239#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
240#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
241#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
242#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
243#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
244#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
245#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
246#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
247#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
248
249/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
250#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
251#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
252#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
253#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
254#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
255#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
256#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
257#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
258#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
259#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
260#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
261#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
262#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
263#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
264#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
265#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
266#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
267
268/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
269#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
270#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
271#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
272#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
273#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
274#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
275#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
276#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
277#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
278#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
279#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
280#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
281#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
282#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
283#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
284#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
285#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
286#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
287#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
288#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
289#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
290#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
291
292/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
293#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
294#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
295#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
296#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
297#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
298#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
299#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
300#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
301#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
302#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
303#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
304#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
305#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
306#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
307#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
308#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
309#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
310#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
311#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
312#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
313#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
314#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
315
316/* Asynchronous Memory Controller - External Bus Interface Unit */
317#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
318#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
319#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
320
321/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
322#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
323#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
324#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
325#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
326
327/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
328#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
329#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
330#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
331#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
332#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
333
334/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
335#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
336#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
337#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
338#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
339#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
340
341/*DMA traffic control registers */
342#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */
343#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
344#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */
345#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */
346
347/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
348#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
349#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
350#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
351#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
352#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
353#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
354#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
355#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
356#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
357#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
358#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
359#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
360#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
361
362#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
363#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
364#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
365#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
366#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
367#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
368#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
369#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
370#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
371#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
372#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
373#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
374#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
375
376#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
377#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
378#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
379#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
380#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
381#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
382#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
383#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
384#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
385#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
386#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
387#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
388#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
389
390#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
391#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
392#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
393#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
394#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
395#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
396#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
397#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
398#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
399#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
400#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
401#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
402#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
403
404#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
405#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
406#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
407#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
408#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
409#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
410#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
411#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
412#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
413#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
414#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
415#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
416#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
417
418#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
419#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
420#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
421#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
422#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
423#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
424#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
425#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
426#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
427#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
428#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
429#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
430#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
431
432#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
433#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
434#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
435#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
436#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
437#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
438#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
439#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
440#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
441#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
442#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
443#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
444#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
445
446#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
447#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
448#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
449#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
450#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
451#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
452#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
453#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
454#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
455#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
456#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
457#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
458#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
459
460#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
461#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
462#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
463#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
464#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
465#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
466#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
467#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
468#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
469#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
470#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
471#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
472#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
473
474#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
475#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
476#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
477#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
478#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
479#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
480#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
481#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
482#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
483#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
484#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
485#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
486#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
487
488#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
489#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
490#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
491#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
492#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
493#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
494#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
495#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
496#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
497#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
498#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
499#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
500#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
501
502#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
503#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
504#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
505#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
506#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
507#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
508#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
509#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
510#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
511#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
512#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
513#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
514#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
515
516/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
517#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
518#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
519#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
520#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
521#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
522#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
523#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
524#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
525#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
526#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
527#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
528#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
529#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
530
531#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
532#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
533#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
534#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
535#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
536#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
537#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
538#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
539#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
540#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
541#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
542#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
543#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
544
545#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
546#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
547#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
548#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
549#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
550#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
551#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
552#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
553#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
554#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
555#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
556#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
557#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
558
559#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
560#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
561#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
562#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
563#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
564#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
565#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
566#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
567#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
568#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
569#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
570#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
571#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
572
573/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
574#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
575#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
576#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
577#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
578#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
579#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
580#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
581#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
582#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
583#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
584#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
585#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
586#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
587
588#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
589#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
590#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
591#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
592#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
593#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
594#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
595#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
596#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
597#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
598#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
599#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
600#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
601
602#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
603#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
604#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
605#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
606#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
607#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
608#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
609#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
610#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
611#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
612#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
613#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
614#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
615
616#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
617#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
618#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
619#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
620#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
621#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
622#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
623#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
624#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
625#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
626#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
627#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
628#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
629
630#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
631#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
632#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
633#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
634#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
635#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
636#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
637#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
638#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
639#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
640#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
641#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
642#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
643
644#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
645#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
646#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
647#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
648#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
649#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
650#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
651#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
652#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
653#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
654#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
655#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
656#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
657
658#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
659#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
660#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
661#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
662#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
663#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
664#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
665#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
666#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
667#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
668#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
669#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
670#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
671
672#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
673#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
674#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
675#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
676#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
677#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
678#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
679#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
680#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
681#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
682#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
683#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
684#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
685
686#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
687#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
688#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
689#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
690#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
691#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
692#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
693#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
694#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
695#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
696#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
697#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
698#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
699
700#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
701#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
702#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
703#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
704#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
705#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
706#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
707#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
708#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
709#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
710#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
711#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
712#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
713
714#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
715#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
716#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
717#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
718#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
719#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
720#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
721#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
722#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
723#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
724#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
725#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
726#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
727
728#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
729#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
730#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
731#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
732#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
733#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
734#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
735#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
736#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
737#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
738#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
739#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
740#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
741
742/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
743#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
744#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
745#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
746#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
747#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
748#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
749#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
750#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
751#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
752#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
753#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
754#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
755#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
756
757#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
758#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
759#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
760#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
761#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
762#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
763#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
764#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
765#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
766#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
767#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
768#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
769#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
770
771#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
772#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
773#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
774#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
775#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
776#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
777#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
778#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
779#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
780#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
781#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
782#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
783#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
784
785#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
786#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
787#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
788#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
789#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
790#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
791#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
792#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
793#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
794#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
795#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
796#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
797#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
798
799/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
800#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
801#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
802#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
803#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
804#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
805#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
806#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
807#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
808#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
809#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
810#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
811#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
812
813#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
814#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
815#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
816#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
817#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
818#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
819#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
820#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
821#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
822#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
823#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
824#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
825
826#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
827#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
828#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
829#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
830#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
831#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
832#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
833#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
834#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
835#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
836#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
837#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
838
839#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
840#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
841#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
842#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
843#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
844#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
845#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
846#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
847#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
848#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
849#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
850#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
851
852/*********************************************************************************** */
853/* System MMR Register Bits */
854/******************************************************************************* */
855
856/* ********************* PLL AND RESET MASKS ************************ */
857
858/* PLL_CTL Masks */
859#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
860#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
861#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
862#define STOPCK_OFF 0x00000008 /* Core clock off */
863#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
864#define BYPASS 0x00000100 /* Bypass the PLL */
865
866/* CHIPID Masks */
867#define CHIPID_VERSION 0xF0000000
868#define CHIPID_FAMILY 0x0FFFF000
869#define CHIPID_MANUFACTURE 0x00000FFE
870
871/* VR_CTL Masks */
872#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
873#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
874#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
875#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
876#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
877
878#define GAIN 0x000C /* Voltage Level Gain */
879#define GAIN_5 0x0000 /* GAIN = 5*/
880#define GAIN_10 0x0004 /* GAIN = 1*/
881#define GAIN_20 0x0008 /* GAIN = 2*/
882#define GAIN_50 0x000C /* GAIN = 5*/
883
884#define VLEV 0x00F0 /* Internal Voltage Level */
885#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
886#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
887#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
888#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
889#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
890#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
891#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
892#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
893#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
894#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
895
896#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
897#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
898
899/* PLL_DIV Masks */
900#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
901
902#define CSEL 0x30 /* Core Select */
903#define SSEL 0xf /* System Select */
904#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
905#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
906#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
907#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
908
909/* PLL_STAT Masks */
910#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
911#define FULL_ON 0x0002 /* Processor In Full On Mode */
912#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
913#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
914
915/* SWRST Mask */
916#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
917#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
918#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
919#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
920#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
921#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
922#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
923#define SWRST_OCCURRED 0x8000 /* SWRST Status */
924
925/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
926
927/* SICu_IARv Masks */
928/* u = A or B */
929/* v = 0 to 7 */
930/* w = 0 or 1 */
931
932/* Per_number = 0 to 63 */
933/* IVG_number = 7 to 15 */
934#define Peripheral_IVG(Per_number, IVG_number) \
935 ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */
936 /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
937 /* r0.h = hi(Peripheral_IVG(62, 10)); */
938
939/* SICx_IMASKw Masks */
940/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
941#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
942#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
943#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
944#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
945
946/* SIC_IWR Masks */
947#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
948#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
949/* x = pos 0 to 31, for 32-63 use value-32 */
950#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
951#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
952
953/* ***************************** UART CONTROLLER MASKS ********************** */
954
955/* UART_LCR Register */
956
957#define DLAB 0x80
958#define SB 0x40
959#define STP 0x20
960#define EPS 0x10
961#define PEN 0x08
962#define STB 0x04
963#define WLS(x) ((x-5) & 0x03)
964
965#define DLAB_P 0x07
966#define SB_P 0x06
967#define STP_P 0x05
968#define EPS_P 0x04
969#define PEN_P 0x03
970#define STB_P 0x02
971#define WLS_P1 0x01
972#define WLS_P0 0x00
973
974/* UART_MCR Register */
975#define LOOP_ENA 0x10
976#define LOOP_ENA_P 0x04
977
978/* UART_LSR Register */
979#define TEMT 0x40
980#define THRE 0x20
981#define BI 0x10
982#define FE 0x08
983#define PE 0x04
984#define OE 0x02
985#define DR 0x01
986
987#define TEMP_P 0x06
988#define THRE_P 0x05
989#define BI_P 0x04
990#define FE_P 0x03
991#define PE_P 0x02
992#define OE_P 0x01
993#define DR_P 0x00
994
995/* UART_IER Register */
996#define ELSI 0x04
997#define ETBEI 0x02
998#define ERBFI 0x01
999
1000#define ELSI_P 0x02
1001#define ETBEI_P 0x01
1002#define ERBFI_P 0x00
1003
1004/* UART_IIR Register */
1005#define STATUS(x) ((x << 1) & 0x06)
1006#define NINT 0x01
1007#define STATUS_P1 0x02
1008#define STATUS_P0 0x01
1009#define NINT_P 0x00
1010#define IIR_TX_READY 0x02 /* UART_THR empty */
1011#define IIR_RX_READY 0x04 /* Receive data ready */
1012#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1013#define IIR_STATUS 0x06
1014
1015/* UART_GCTL Register */
1016#define FFE 0x20
1017#define FPE 0x10
1018#define RPOLC 0x08
1019#define TPOLC 0x04
1020#define IREN 0x02
1021#define UCEN 0x01
1022
1023#define FFE_P 0x05
1024#define FPE_P 0x04
1025#define RPOLC_P 0x03
1026#define TPOLC_P 0x02
1027#define IREN_P 0x01
1028#define UCEN_P 0x00
1029
1030/* ********** SERIAL PORT MASKS ********************** */
1031
1032/* SPORTx_TCR1 Masks */
1033#define TSPEN 0x0001 /* TX enable */
1034#define ITCLK 0x0002 /* Internal TX Clock Select */
1035#define TDTYPE 0x000C /* TX Data Formatting Select */
1036#define TLSBIT 0x0010 /* TX Bit Order */
1037#define ITFS 0x0200 /* Internal TX Frame Sync Select */
1038#define TFSR 0x0400 /* TX Frame Sync Required Select */
1039#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
1040#define LTFS 0x1000 /* Low TX Frame Sync Select */
1041#define LATFS 0x2000 /* Late TX Frame Sync Select */
1042#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
1043
1044/* SPORTx_TCR2 Masks */
1045#define SLEN 0x001F /*TX Word Length */
1046#define TXSE 0x0100 /*TX Secondary Enable */
1047#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
1048#define TRFST 0x0400 /*TX Right-First Data Order */
1049
1050/* SPORTx_RCR1 Masks */
1051#define RSPEN 0x0001 /* RX enable */
1052#define IRCLK 0x0002 /* Internal RX Clock Select */
1053#define RDTYPE 0x000C /* RX Data Formatting Select */
1054#define RULAW 0x0008 /* u-Law enable */
1055#define RALAW 0x000C /* A-Law enable */
1056#define RLSBIT 0x0010 /* RX Bit Order */
1057#define IRFS 0x0200 /* Internal RX Frame Sync Select */
1058#define RFSR 0x0400 /* RX Frame Sync Required Select */
1059#define LRFS 0x1000 /* Low RX Frame Sync Select */
1060#define LARFS 0x2000 /* Late RX Frame Sync Select */
1061#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
1062
1063/* SPORTx_RCR2 Masks */
1064#define SLEN 0x001F /*RX Word Length */
1065#define RXSE 0x0100 /*RX Secondary Enable */
1066#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
1067#define RRFST 0x0400 /*Right-First Data Order */
1068
1069/*SPORTx_STAT Masks */
1070#define RXNE 0x0001 /*RX FIFO Not Empty Status */
1071#define RUVF 0x0002 /*RX Underflow Status */
1072#define ROVF 0x0004 /*RX Overflow Status */
1073#define TXF 0x0008 /*TX FIFO Full Status */
1074#define TUVF 0x0010 /*TX Underflow Status */
1075#define TOVF 0x0020 /*TX Overflow Status */
1076#define TXHRE 0x0040 /*TX Hold Register Empty */
1077
1078/*SPORTx_MCMC1 Masks */
1079#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
1080#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
1081
1082/*SPORTx_MCMC2 Masks */
1083#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
1084#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
1085#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
1086#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
1087#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
1088#define MFD 0x0000F000 /*Multichannel Frame Delay */
1089
1090/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1091
1092/* PPI_CONTROL Masks */
1093#define PORT_EN 0x00000001 /* PPI Port Enable */
1094#define PORT_DIR 0x00000002 /* PPI Port Direction */
1095#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
1096#define PORT_CFG 0x00000030 /* PPI Port Configuration */
1097#define FLD_SEL 0x00000040 /* PPI Active Field Select */
1098#define PACK_EN 0x00000080 /* PPI Packing Mode */
1099#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
1100#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
1101#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
1102#define DLENGTH 0x00003800 /* PPI Data Length */
1103#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
1104#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1105#define POL 0x0000C000 /* PPI Signal Polarities */
1106
1107/* PPI_STATUS Masks */
1108#define FLD 0x00000400 /* Field Indicator */
1109#define FT_ERR 0x00000800 /* Frame Track Error */
1110#define OVR 0x00001000 /* FIFO Overflow Error */
1111#define UNDR 0x00002000 /* FIFO Underrun Error */
1112#define ERR_DET 0x00004000 /* Error Detected Indicator */
1113#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
1114
1115/* ********** DMA CONTROLLER MASKS *********************8 */
1116
1117/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
1118#define DMAEN 0x00000001 /* Channel Enable */
1119#define WNR 0x00000002 /* Channel Direction (W/R*) */
1120#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
1121#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
1122#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
1123#define DMA2D 0x00000010 /* 2D/1D* Mode */
1124#define RESTART 0x00000020 /* Restart */
1125#define DI_SEL 0x00000040 /* Data Interrupt Select */
1126#define DI_EN 0x00000080 /* Data Interrupt Enable */
1127#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1128#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1129#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1130#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1131#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1132#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1133#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1134#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1135#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1136#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1137#define NDSIZE 0x00000900 /* Next Descriptor Size */
1138#define DMAFLOW 0x00007000 /* Flow Control */
1139#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1140#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1141#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1142#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1143#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1144
1145#define DMAEN_P 0 /* Channel Enable */
1146#define WNR_P 1 /* Channel Direction (W/R*) */
1147#define DMA2D_P 4 /* 2D/1D* Mode */
1148#define RESTART_P 5 /* Restart */
1149#define DI_SEL_P 6 /* Data Interrupt Select */
1150#define DI_EN_P 7 /* Data Interrupt Enable */
1151
1152/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
1153
1154#define DMA_DONE 0x00000001 /* DMA Done Indicator */
1155#define DMA_ERR 0x00000002 /* DMA Error Indicator */
1156#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
1157#define DMA_RUN 0x00000008 /* DMA Running Indicator */
1158
1159#define DMA_DONE_P 0 /* DMA Done Indicator */
1160#define DMA_ERR_P 1 /* DMA Error Indicator */
1161#define DFETCH_P 2 /* Descriptor Fetch Indicator */
1162#define DMA_RUN_P 3 /* DMA Running Indicator */
1163
1164/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
1165
1166#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
1167#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
1168#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
1169#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
1170#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
1171#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
1172#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
1173#define PMAP 0x00007000 /* DMA Peripheral Map Field */
1174
1175/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
1176
1177/* PWM Timer bit definitions */
1178
1179/* TIMER_ENABLE Register */
1180#define TIMEN0 0x0001
1181#define TIMEN1 0x0002
1182#define TIMEN2 0x0004
1183#define TIMEN3 0x0008
1184#define TIMEN4 0x0010
1185#define TIMEN5 0x0020
1186#define TIMEN6 0x0040
1187#define TIMEN7 0x0080
1188#define TIMEN8 0x0001
1189#define TIMEN9 0x0002
1190#define TIMEN10 0x0004
1191#define TIMEN11 0x0008
1192
1193#define TIMEN0_P 0x00
1194#define TIMEN1_P 0x01
1195#define TIMEN2_P 0x02
1196#define TIMEN3_P 0x03
1197#define TIMEN4_P 0x04
1198#define TIMEN5_P 0x05
1199#define TIMEN6_P 0x06
1200#define TIMEN7_P 0x07
1201#define TIMEN8_P 0x00
1202#define TIMEN9_P 0x01
1203#define TIMEN10_P 0x02
1204#define TIMEN11_P 0x03
1205
1206/* TIMER_DISABLE Register */
1207#define TIMDIS0 0x0001
1208#define TIMDIS1 0x0002
1209#define TIMDIS2 0x0004
1210#define TIMDIS3 0x0008
1211#define TIMDIS4 0x0010
1212#define TIMDIS5 0x0020
1213#define TIMDIS6 0x0040
1214#define TIMDIS7 0x0080
1215#define TIMDIS8 0x0001
1216#define TIMDIS9 0x0002
1217#define TIMDIS10 0x0004
1218#define TIMDIS11 0x0008
1219
1220#define TIMDIS0_P 0x00
1221#define TIMDIS1_P 0x01
1222#define TIMDIS2_P 0x02
1223#define TIMDIS3_P 0x03
1224#define TIMDIS4_P 0x04
1225#define TIMDIS5_P 0x05
1226#define TIMDIS6_P 0x06
1227#define TIMDIS7_P 0x07
1228#define TIMDIS8_P 0x00
1229#define TIMDIS9_P 0x01
1230#define TIMDIS10_P 0x02
1231#define TIMDIS11_P 0x03
1232
1233/* TIMER_STATUS Register */
1234#define TIMIL0 0x00000001
1235#define TIMIL1 0x00000002
1236#define TIMIL2 0x00000004
1237#define TIMIL3 0x00000008
1238#define TIMIL4 0x00010000
1239#define TIMIL5 0x00020000
1240#define TIMIL6 0x00040000
1241#define TIMIL7 0x00080000
1242#define TIMIL8 0x0001
1243#define TIMIL9 0x0002
1244#define TIMIL10 0x0004
1245#define TIMIL11 0x0008
1246#define TOVF_ERR0 0x00000010
1247#define TOVF_ERR1 0x00000020
1248#define TOVF_ERR2 0x00000040
1249#define TOVF_ERR3 0x00000080
1250#define TOVF_ERR4 0x00100000
1251#define TOVF_ERR5 0x00200000
1252#define TOVF_ERR6 0x00400000
1253#define TOVF_ERR7 0x00800000
1254#define TOVF_ERR8 0x0010
1255#define TOVF_ERR9 0x0020
1256#define TOVF_ERR10 0x0040
1257#define TOVF_ERR11 0x0080
1258#define TRUN0 0x00001000
1259#define TRUN1 0x00002000
1260#define TRUN2 0x00004000
1261#define TRUN3 0x00008000
1262#define TRUN4 0x10000000
1263#define TRUN5 0x20000000
1264#define TRUN6 0x40000000
1265#define TRUN7 0x80000000
1266#define TRUN8 0x1000
1267#define TRUN9 0x2000
1268#define TRUN10 0x4000
1269#define TRUN11 0x8000
1270
1271#define TIMIL0_P 0x00
1272#define TIMIL1_P 0x01
1273#define TIMIL2_P 0x02
1274#define TIMIL3_P 0x03
1275#define TIMIL4_P 0x10
1276#define TIMIL5_P 0x11
1277#define TIMIL6_P 0x12
1278#define TIMIL7_P 0x13
1279#define TIMIL8_P 0x00
1280#define TIMIL9_P 0x01
1281#define TIMIL10_P 0x02
1282#define TIMIL11_P 0x03
1283#define TOVF_ERR0_P 0x04
1284#define TOVF_ERR1_P 0x05
1285#define TOVF_ERR2_P 0x06
1286#define TOVF_ERR3_P 0x07
1287#define TOVF_ERR4_P 0x14
1288#define TOVF_ERR5_P 0x15
1289#define TOVF_ERR6_P 0x16
1290#define TOVF_ERR7_P 0x17
1291#define TOVF_ERR8_P 0x04
1292#define TOVF_ERR9_P 0x05
1293#define TOVF_ERR10_P 0x06
1294#define TOVF_ERR11_P 0x07
1295#define TRUN0_P 0x0C
1296#define TRUN1_P 0x0D
1297#define TRUN2_P 0x0E
1298#define TRUN3_P 0x0F
1299#define TRUN4_P 0x1C
1300#define TRUN5_P 0x1D
1301#define TRUN6_P 0x1E
1302#define TRUN7_P 0x1F
1303#define TRUN8_P 0x0C
1304#define TRUN9_P 0x0D
1305#define TRUN10_P 0x0E
1306#define TRUN11_P 0x0F
1307
1308/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1309#define TOVL_ERR0 TOVF_ERR0
1310#define TOVL_ERR1 TOVF_ERR1
1311#define TOVL_ERR2 TOVF_ERR2
1312#define TOVL_ERR3 TOVF_ERR3
1313#define TOVL_ERR4 TOVF_ERR4
1314#define TOVL_ERR5 TOVF_ERR5
1315#define TOVL_ERR6 TOVF_ERR6
1316#define TOVL_ERR7 TOVF_ERR7
1317#define TOVL_ERR8 TOVF_ERR8
1318#define TOVL_ERR9 TOVF_ERR9
1319#define TOVL_ERR10 TOVF_ERR10
1320#define TOVL_ERR11 TOVF_ERR11
1321#define TOVL_ERR0_P TOVF_ERR0_P
1322#define TOVL_ERR1_P TOVF_ERR1_P
1323#define TOVL_ERR2_P TOVF_ERR2_P
1324#define TOVL_ERR3_P TOVF_ERR3_P
1325#define TOVL_ERR4_P TOVF_ERR4_P
1326#define TOVL_ERR5_P TOVF_ERR5_P
1327#define TOVL_ERR6_P TOVF_ERR6_P
1328#define TOVL_ERR7_P TOVF_ERR7_P
1329#define TOVL_ERR8_P TOVF_ERR8_P
1330#define TOVL_ERR9_P TOVF_ERR9_P
1331#define TOVL_ERR10_P TOVF_ERR10_P
1332#define TOVL_ERR11_P TOVF_ERR11_P
1333
1334/* TIMERx_CONFIG Registers */
1335#define PWM_OUT 0x0001
1336#define WDTH_CAP 0x0002
1337#define EXT_CLK 0x0003
1338#define PULSE_HI 0x0004
1339#define PERIOD_CNT 0x0008
1340#define IRQ_ENA 0x0010
1341#define TIN_SEL 0x0020
1342#define OUT_DIS 0x0040
1343#define CLK_SEL 0x0080
1344#define TOGGLE_HI 0x0100
1345#define EMU_RUN 0x0200
1346#define ERR_TYP(x) ((x & 0x03) << 14)
1347
1348#define TMODE_P0 0x00
1349#define TMODE_P1 0x01
1350#define PULSE_HI_P 0x02
1351#define PERIOD_CNT_P 0x03
1352#define IRQ_ENA_P 0x04
1353#define TIN_SEL_P 0x05
1354#define OUT_DIS_P 0x06
1355#define CLK_SEL_P 0x07
1356#define TOGGLE_HI_P 0x08
1357#define EMU_RUN_P 0x09
1358#define ERR_TYP_P0 0x0E
1359#define ERR_TYP_P1 0x0F
1360
1361/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
1362
1363/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1364#define PF0 0x0001
1365#define PF1 0x0002
1366#define PF2 0x0004
1367#define PF3 0x0008
1368#define PF4 0x0010
1369#define PF5 0x0020
1370#define PF6 0x0040
1371#define PF7 0x0080
1372#define PF8 0x0100
1373#define PF9 0x0200
1374#define PF10 0x0400
1375#define PF11 0x0800
1376#define PF12 0x1000
1377#define PF13 0x2000
1378#define PF14 0x4000
1379#define PF15 0x8000
1380
1381/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
1382#define PF0_P 0
1383#define PF1_P 1
1384#define PF2_P 2
1385#define PF3_P 3
1386#define PF4_P 4
1387#define PF5_P 5
1388#define PF6_P 6
1389#define PF7_P 7
1390#define PF8_P 8
1391#define PF9_P 9
1392#define PF10_P 10
1393#define PF11_P 11
1394#define PF12_P 12
1395#define PF13_P 13
1396#define PF14_P 14
1397#define PF15_P 15
1398
1399/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
1400
1401/* SPI_CTL Masks */
1402#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
1403#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
1404#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
1405#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
1406#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
1407#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
1408#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
1409#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
1410#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
1411#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
1412#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
1413#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
1414
1415/* SPI_FLG Masks */
1416#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1417#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1418#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1419#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1420#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1421#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1422#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1423#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1424#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1425#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1426#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1427#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1428#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1429#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1430
1431/* SPI_FLG Bit Positions */
1432#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1433#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1434#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1435#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1436#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1437#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1438#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1439#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1440#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1441#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1442#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1443#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1444#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1445#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1446
1447/* SPI_STAT Masks */
1448#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
1449#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
1450#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1451#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1452#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
1453#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
1454#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
1455
1456/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1457
1458/* AMGCTL Masks */
1459#define AMCKEN 0x0001 /* Enable CLKOUT */
1460#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
1461#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
1462#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1463#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1464#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
1465#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
1466#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
1467#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
1468
1469/* AMGCTL Bit Positions */
1470#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
1471#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1472#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1473#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1474#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */
1475#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */
1476#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */
1477#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */
1478
1479/* AMBCTL0 Masks */
1480#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
1481#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
1482#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
1483#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1484#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1485#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1486#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1487#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1488#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1489#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1490#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1491#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1492#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1493#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1494#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
1495#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1496#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1497#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1498#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1499#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1500#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1501#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1502#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1503#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1504#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1505#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1506#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1507#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1508#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1509#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
1510#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1511#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1512#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1513#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1514#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1515#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1516#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1517#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1518#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1519#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1520#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1521#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1522#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1523#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1524#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
1525#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
1526#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
1527#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1528#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1529#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1530#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1531#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1532#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1533#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1534#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1535#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1536#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1537#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1538#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
1539#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1540#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1541#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1542#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1543#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1544#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1545#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1546#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1547#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1548#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1549#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1550#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1551#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1552#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1553#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1554#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1555#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1556#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1557#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1558#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1559#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1560#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1561#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1562#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1563#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1564#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
1565#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
1566#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1567#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1568
1569/* AMBCTL1 Masks */
1570#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1571#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1572#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1573#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1574#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1575#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1576#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1577#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1578#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1579#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1580#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1581#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1582#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1583#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1584#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1585#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1586#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1587#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1588#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1589#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1590#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1591#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1592#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1593#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1594#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1595#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1596#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1597#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1598#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1599#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1600#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1601#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1602#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1603#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1604#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1605#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1606#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1607#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1608#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1609#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1610#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1611#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1612#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1613#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1614#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1615#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1616#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1617#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1618#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1619#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1620#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1621#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1622#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1623#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1624#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1625#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1626#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1627#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1628#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1629#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1630#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1631#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1632#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1633#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1634#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1635#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1636#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1637#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1638#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1639#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1640#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1641#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1642#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1643#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1644#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1645#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1646#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1647#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1648#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1649#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1650#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1651#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1652#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1653#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1654#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1655#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1656#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1657#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1658
1659/* ********************** SDRAM CONTROLLER MASKS *************************** */
1660
1661/* EBIU_SDGCTL Masks */
1662#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1663#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1664#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1665#define PFE 0x00000010 /* Enable SDRAM prefetch */
1666#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1667#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1668#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1669#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1670#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1671#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1672#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1673#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1674#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1675#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1676#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1677#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1678#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1679#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1680#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1681#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1682#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1683#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1684#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1685#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1686#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1687#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1688#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1689#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1690#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1691#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1692#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1693#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1694#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1695#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1696#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1697#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1698#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1699#define PUPSD 0x00200000 /*Power-up start delay */
1700#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1701#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1702#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1703#define EBUFE 0x02000000 /* Enable external buffering timing */
1704#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1705#define EMREN 0x10000000 /* Extended mode register enable */
1706#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1707#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1708
1709/* EBIU_SDBCTL Masks */
1710#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
1711#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1712#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1713#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1714#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1715#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1716#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1717#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1718#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1719
1720#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
1721#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1722#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
1723#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
1724#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
1725#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1726#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
1727#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
1728#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
1729
1730#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
1731#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1732#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
1733#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
1734#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
1735#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1736#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
1737#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
1738#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
1739
1740#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
1741#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1742#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
1743#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
1744#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
1745#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1746#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
1747#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
1748#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
1749
1750/* EBIU_SDSTAT Masks */
1751#define SDCI 0x00000001 /* SDRAM controller is idle */
1752#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1753#define SDPUA 0x00000004 /* SDRAM power up active */
1754#define SDRS 0x00000008 /* SDRAM is in reset state */
1755#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1756#define BGSTAT 0x00000020 /* Bus granted */
1757
1758#endif /* _DEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h
new file mode 100644
index 000000000000..8bc46cd89a02
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/dma.h
@@ -0,0 +1,35 @@
1/*****************************************************************************
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6
7#ifndef _MACH_DMA_H_
8#define _MACH_DMA_H_
9
10#define MAX_BLACKFIN_DMA_CHANNEL 36
11
12#define CH_PPI0 0
13#define CH_PPI (CH_PPI0)
14#define CH_PPI1 1
15#define CH_SPORT0_RX 12
16#define CH_SPORT0_TX 13
17#define CH_SPORT1_RX 14
18#define CH_SPORT1_TX 15
19#define CH_SPI 16
20#define CH_UART_RX 17
21#define CH_UART_TX 18
22#define CH_MEM_STREAM0_DEST 24 /* TX */
23#define CH_MEM_STREAM0_SRC 25 /* RX */
24#define CH_MEM_STREAM1_DEST 26 /* TX */
25#define CH_MEM_STREAM1_SRC 27 /* RX */
26#define CH_MEM_STREAM2_DEST 28
27#define CH_MEM_STREAM2_SRC 29
28#define CH_MEM_STREAM3_DEST 30
29#define CH_MEM_STREAM3_SRC 31
30#define CH_IMEM_STREAM0_DEST 32
31#define CH_IMEM_STREAM0_SRC 33
32#define CH_IMEM_STREAM1_DEST 34
33#define CH_IMEM_STREAM1_SRC 35
34
35#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
new file mode 100644
index 000000000000..6698389c5564
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/irq.h
@@ -0,0 +1,447 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf561/irq.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _BF561_IRQ_H_
33#define _BF561_IRQ_H_
34
35/***********************************************************************
36 * Interrupt source definitions:
37 Event Source Core Event Name IRQ No
38 (highest priority)
39 Emulation Events EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47 PLL Wakeup Interrupt IVG7 7
48 DMA1 Error (generic) IVG7 8
49 DMA2 Error (generic) IVG7 9
50 IMDMA Error (generic) IVG7 10
51 PPI1 Error Interrupt IVG7 11
52 PPI2 Error Interrupt IVG7 12
53 SPORT0 Error Interrupt IVG7 13
54 SPORT1 Error Interrupt IVG7 14
55 SPI Error Interrupt IVG7 15
56 UART Error Interrupt IVG7 16
57 Reserved Interrupt IVG7 17
58
59 DMA1 0 Interrupt(PPI1) IVG8 18
60 DMA1 1 Interrupt(PPI2) IVG8 19
61 DMA1 2 Interrupt IVG8 20
62 DMA1 3 Interrupt IVG8 21
63 DMA1 4 Interrupt IVG8 22
64 DMA1 5 Interrupt IVG8 23
65 DMA1 6 Interrupt IVG8 24
66 DMA1 7 Interrupt IVG8 25
67 DMA1 8 Interrupt IVG8 26
68 DMA1 9 Interrupt IVG8 27
69 DMA1 10 Interrupt IVG8 28
70 DMA1 11 Interrupt IVG8 29
71
72 DMA2 0 (SPORT0 RX) IVG9 30
73 DMA2 1 (SPORT0 TX) IVG9 31
74 DMA2 2 (SPORT1 RX) IVG9 32
75 DMA2 3 (SPORT2 TX) IVG9 33
76 DMA2 4 (SPI) IVG9 34
77 DMA2 5 (UART RX) IVG9 35
78 DMA2 6 (UART TX) IVG9 36
79 DMA2 7 Interrupt IVG9 37
80 DMA2 8 Interrupt IVG9 38
81 DMA2 9 Interrupt IVG9 39
82 DMA2 10 Interrupt IVG9 40
83 DMA2 11 Interrupt IVG9 41
84
85 TIMER 0 Interrupt IVG10 42
86 TIMER 1 Interrupt IVG10 43
87 TIMER 2 Interrupt IVG10 44
88 TIMER 3 Interrupt IVG10 45
89 TIMER 4 Interrupt IVG10 46
90 TIMER 5 Interrupt IVG10 47
91 TIMER 6 Interrupt IVG10 48
92 TIMER 7 Interrupt IVG10 49
93 TIMER 8 Interrupt IVG10 50
94 TIMER 9 Interrupt IVG10 51
95 TIMER 10 Interrupt IVG10 52
96 TIMER 11 Interrupt IVG10 53
97
98 Programmable Flags0 A (8) IVG11 54
99 Programmable Flags0 B (8) IVG11 55
100 Programmable Flags1 A (8) IVG11 56
101 Programmable Flags1 B (8) IVG11 57
102 Programmable Flags2 A (8) IVG11 58
103 Programmable Flags2 B (8) IVG11 59
104
105 MDMA1 0 write/read INT IVG8 60
106 MDMA1 1 write/read INT IVG8 61
107
108 MDMA2 0 write/read INT IVG9 62
109 MDMA2 1 write/read INT IVG9 63
110
111 IMDMA 0 write/read INT IVG12 64
112 IMDMA 1 write/read INT IVG12 65
113
114 Watch Dog Timer IVG13 66
115
116 Reserved interrupt IVG7 67
117 Reserved interrupt IVG7 68
118 Supplemental interrupt 0 IVG7 69
119 supplemental interrupt 1 IVG7 70
120
121 Softirq IVG14
122 System Call --
123 (lowest priority) IVG15
124
125 **********************************************************************/
126
127#define SYS_IRQS 71
128#define NR_PERI_INTS 64
129
130/*
131 * The ABSTRACT IRQ definitions
132 * the first seven of the following are fixed,
133 * the rest you change if you need to.
134 */
135/* IVG 0-6*/
136#define IRQ_EMU 0 /* Emulation */
137#define IRQ_RST 1 /* Reset */
138#define IRQ_NMI 2 /* Non Maskable Interrupt */
139#define IRQ_EVX 3 /* Exception */
140#define IRQ_UNUSED 4 /* Reserved interrupt */
141#define IRQ_HWERR 5 /* Hardware Error */
142#define IRQ_CORETMR 6 /* Core timer */
143
144#define IVG_BASE 7
145/* IVG 7 */
146#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
147#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
148#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
149#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
150#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
151#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
152#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
153#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
154#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
155#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
156#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
157#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
158#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
159/* IVG 8 */
160#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
161#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
162#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
163#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
164#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
165#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
166#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
167#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
168#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
169#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
170#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
171#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
172#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
173#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
174#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
175/* IVG 9 */
176#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
177#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
178#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
179#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
180#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
181#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
182#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
183#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
184#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
185#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
186#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
187#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
188#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
189#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
190#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
191#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
192#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
193#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
194#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
195/* IVG 10 */
196#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
197#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
198#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
199#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
200#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
201#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
202#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
203#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
204#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
205#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
206#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
207#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
208/* IVG 11 */
209#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
210#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
211#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
212#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
213#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
214#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
215#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
216#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
217/* IVG 8 */
218#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
219#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
220#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
221#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
222#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
223#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
224/* IVG 9 */
225#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
226#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
227#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
228#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
229/* IVG 12 */
230#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
231#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
232#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
233#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
234/* IVG 13 */
235#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
236/* IVG 7 */
237#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
238#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
239#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
240#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
241
242#define IRQ_PF0 73
243#define IRQ_PF1 74
244#define IRQ_PF2 75
245#define IRQ_PF3 76
246#define IRQ_PF4 77
247#define IRQ_PF5 78
248#define IRQ_PF6 79
249#define IRQ_PF7 80
250#define IRQ_PF8 81
251#define IRQ_PF9 82
252#define IRQ_PF10 83
253#define IRQ_PF11 84
254#define IRQ_PF12 85
255#define IRQ_PF13 86
256#define IRQ_PF14 87
257#define IRQ_PF15 88
258#define IRQ_PF16 89
259#define IRQ_PF17 90
260#define IRQ_PF18 91
261#define IRQ_PF19 92
262#define IRQ_PF20 93
263#define IRQ_PF21 94
264#define IRQ_PF22 95
265#define IRQ_PF23 96
266#define IRQ_PF24 97
267#define IRQ_PF25 98
268#define IRQ_PF26 99
269#define IRQ_PF27 100
270#define IRQ_PF28 101
271#define IRQ_PF29 102
272#define IRQ_PF30 103
273#define IRQ_PF31 104
274#define IRQ_PF32 105
275#define IRQ_PF33 106
276#define IRQ_PF34 107
277#define IRQ_PF35 108
278#define IRQ_PF36 109
279#define IRQ_PF37 110
280#define IRQ_PF38 111
281#define IRQ_PF39 112
282#define IRQ_PF40 113
283#define IRQ_PF41 114
284#define IRQ_PF42 115
285#define IRQ_PF43 116
286#define IRQ_PF44 117
287#define IRQ_PF45 118
288#define IRQ_PF46 119
289#define IRQ_PF47 120
290
291#define GPIO_IRQ_BASE IRQ_PF0
292
293#define NR_IRQS (IRQ_PF47 + 1)
294
295#define IVG7 7
296#define IVG8 8
297#define IVG9 9
298#define IVG10 10
299#define IVG11 11
300#define IVG12 12
301#define IVG13 13
302#define IVG14 14
303#define IVG15 15
304
305/*
306 * DEFAULT PRIORITIES:
307 */
308
309#define CONFIG_DEF_PLL_WAKEUP 7
310#define CONFIG_DEF_DMA1_ERROR 7
311#define CONFIG_DEF_DMA2_ERROR 7
312#define CONFIG_DEF_IMDMA_ERROR 7
313#define CONFIG_DEF_PPI1_ERROR 7
314#define CONFIG_DEF_PPI2_ERROR 7
315#define CONFIG_DEF_SPORT0_ERROR 7
316#define CONFIG_DEF_SPORT1_ERROR 7
317#define CONFIG_DEF_SPI_ERROR 7
318#define CONFIG_DEF_UART_ERROR 7
319#define CONFIG_DEF_RESERVED_ERROR 7
320#define CONFIG_DEF_DMA1_0 8
321#define CONFIG_DEF_DMA1_1 8
322#define CONFIG_DEF_DMA1_2 8
323#define CONFIG_DEF_DMA1_3 8
324#define CONFIG_DEF_DMA1_4 8
325#define CONFIG_DEF_DMA1_5 8
326#define CONFIG_DEF_DMA1_6 8
327#define CONFIG_DEF_DMA1_7 8
328#define CONFIG_DEF_DMA1_8 8
329#define CONFIG_DEF_DMA1_9 8
330#define CONFIG_DEF_DMA1_10 8
331#define CONFIG_DEF_DMA1_11 8
332#define CONFIG_DEF_DMA2_0 9
333#define CONFIG_DEF_DMA2_1 9
334#define CONFIG_DEF_DMA2_2 9
335#define CONFIG_DEF_DMA2_3 9
336#define CONFIG_DEF_DMA2_4 9
337#define CONFIG_DEF_DMA2_5 9
338#define CONFIG_DEF_DMA2_6 9
339#define CONFIG_DEF_DMA2_7 9
340#define CONFIG_DEF_DMA2_8 9
341#define CONFIG_DEF_DMA2_9 9
342#define CONFIG_DEF_DMA2_10 9
343#define CONFIG_DEF_DMA2_11 9
344#define CONFIG_DEF_TIMER0 10
345#define CONFIG_DEF_TIMER1 10
346#define CONFIG_DEF_TIMER2 10
347#define CONFIG_DEF_TIMER3 10
348#define CONFIG_DEF_TIMER4 10
349#define CONFIG_DEF_TIMER5 10
350#define CONFIG_DEF_TIMER6 10
351#define CONFIG_DEF_TIMER7 10
352#define CONFIG_DEF_TIMER8 10
353#define CONFIG_DEF_TIMER9 10
354#define CONFIG_DEF_TIMER10 10
355#define CONFIG_DEF_TIMER11 10
356#define CONFIG_DEF_PROG0_INTA 11
357#define CONFIG_DEF_PROG0_INTB 11
358#define CONFIG_DEF_PROG1_INTA 11
359#define CONFIG_DEF_PROG1_INTB 11
360#define CONFIG_DEF_PROG2_INTA 11
361#define CONFIG_DEF_PROG2_INTB 11
362#define CONFIG_DEF_DMA1_WRRD0 8
363#define CONFIG_DEF_DMA1_WRRD1 8
364#define CONFIG_DEF_DMA2_WRRD0 9
365#define CONFIG_DEF_DMA2_WRRD1 9
366#define CONFIG_DEF_IMDMA_WRRD0 12
367#define CONFIG_DEF_IMDMA_WRRD1 12
368#define CONFIG_DEF_WATCH 13
369#define CONFIG_DEF_RESERVED_1 7
370#define CONFIG_DEF_RESERVED_2 7
371#define CONFIG_DEF_SUPPLE_0 7
372#define CONFIG_DEF_SUPPLE_1 7
373
374/* IAR0 BIT FIELDS */
375#define IRQ_PLL_WAKEUP_POS 0
376#define IRQ_DMA1_ERROR_POS 4
377#define IRQ_DMA2_ERROR_POS 8
378#define IRQ_IMDMA_ERROR_POS 12
379#define IRQ_PPI0_ERROR_POS 16
380#define IRQ_PPI1_ERROR_POS 20
381#define IRQ_SPORT0_ERROR_POS 24
382#define IRQ_SPORT1_ERROR_POS 28
383/* IAR1 BIT FIELDS */
384#define IRQ_SPI_ERROR_POS 0
385#define IRQ_UART_ERROR_POS 4
386#define IRQ_RESERVED_ERROR_POS 8
387#define IRQ_DMA1_0_POS 12
388#define IRQ_DMA1_1_POS 16
389#define IRQ_DMA1_2_POS 20
390#define IRQ_DMA1_3_POS 24
391#define IRQ_DMA1_4_POS 28
392/* IAR2 BIT FIELDS */
393#define IRQ_DMA1_5_POS 0
394#define IRQ_DMA1_6_POS 4
395#define IRQ_DMA1_7_POS 8
396#define IRQ_DMA1_8_POS 12
397#define IRQ_DMA1_9_POS 16
398#define IRQ_DMA1_10_POS 20
399#define IRQ_DMA1_11_POS 24
400#define IRQ_DMA2_0_POS 28
401/* IAR3 BIT FIELDS */
402#define IRQ_DMA2_1_POS 0
403#define IRQ_DMA2_2_POS 4
404#define IRQ_DMA2_3_POS 8
405#define IRQ_DMA2_4_POS 12
406#define IRQ_DMA2_5_POS 16
407#define IRQ_DMA2_6_POS 20
408#define IRQ_DMA2_7_POS 24
409#define IRQ_DMA2_8_POS 28
410/* IAR4 BIT FIELDS */
411#define IRQ_DMA2_9_POS 0
412#define IRQ_DMA2_10_POS 4
413#define IRQ_DMA2_11_POS 8
414#define IRQ_TIMER0_POS 12
415#define IRQ_TIMER1_POS 16
416#define IRQ_TIMER2_POS 20
417#define IRQ_TIMER3_POS 24
418#define IRQ_TIMER4_POS 28
419/* IAR5 BIT FIELDS */
420#define IRQ_TIMER5_POS 0
421#define IRQ_TIMER6_POS 4
422#define IRQ_TIMER7_POS 8
423#define IRQ_TIMER8_POS 12
424#define IRQ_TIMER9_POS 16
425#define IRQ_TIMER10_POS 20
426#define IRQ_TIMER11_POS 24
427#define IRQ_PROG0_INTA_POS 28
428/* IAR6 BIT FIELDS */
429#define IRQ_PROG0_INTB_POS 0
430#define IRQ_PROG1_INTA_POS 4
431#define IRQ_PROG1_INTB_POS 8
432#define IRQ_PROG2_INTA_POS 12
433#define IRQ_PROG2_INTB_POS 16
434#define IRQ_DMA1_WRRD0_POS 20
435#define IRQ_DMA1_WRRD1_POS 24
436#define IRQ_DMA2_WRRD0_POS 28
437/* IAR7 BIT FIELDS */
438#define IRQ_DMA2_WRRD1_POS 0
439#define IRQ_IMDMA_WRRD0_POS 4
440#define IRQ_IMDMA_WRRD1_POS 8
441#define IRQ_WDTIMER_POS 12
442#define IRQ_RESERVED_1_POS 16
443#define IRQ_RESERVED_2_POS 20
444#define IRQ_SUPPLE_0_POS 24
445#define IRQ_SUPPLE_1_POS 28
446
447#endif /* _BF561_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_init.h b/arch/blackfin/mach-bf561/include/mach/mem_init.h
new file mode 100644
index 000000000000..e163260bca18
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/mem_init.h
@@ -0,0 +1,295 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
32#if (CONFIG_SCLK_HZ > 119402985)
33#define SDRAM_tRP TRP_2
34#define SDRAM_tRP_num 2
35#define SDRAM_tRAS TRAS_7
36#define SDRAM_tRAS_num 7
37#define SDRAM_tRCD TRCD_2
38#define SDRAM_tWR TWR_2
39#endif
40#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
41#define SDRAM_tRP TRP_2
42#define SDRAM_tRP_num 2
43#define SDRAM_tRAS TRAS_6
44#define SDRAM_tRAS_num 6
45#define SDRAM_tRCD TRCD_2
46#define SDRAM_tWR TWR_2
47#endif
48#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
49#define SDRAM_tRP TRP_2
50#define SDRAM_tRP_num 2
51#define SDRAM_tRAS TRAS_5
52#define SDRAM_tRAS_num 5
53#define SDRAM_tRCD TRCD_2
54#define SDRAM_tWR TWR_2
55#endif
56#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
57#define SDRAM_tRP TRP_2
58#define SDRAM_tRP_num 2
59#define SDRAM_tRAS TRAS_4
60#define SDRAM_tRAS_num 4
61#define SDRAM_tRCD TRCD_2
62#define SDRAM_tWR TWR_2
63#endif
64#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
65#define SDRAM_tRP TRP_2
66#define SDRAM_tRP_num 2
67#define SDRAM_tRAS TRAS_3
68#define SDRAM_tRAS_num 3
69#define SDRAM_tRCD TRCD_2
70#define SDRAM_tWR TWR_2
71#endif
72#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
73#define SDRAM_tRP TRP_1
74#define SDRAM_tRP_num 1
75#define SDRAM_tRAS TRAS_4
76#define SDRAM_tRAS_num 3
77#define SDRAM_tRCD TRCD_1
78#define SDRAM_tWR TWR_2
79#endif
80#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
81#define SDRAM_tRP TRP_1
82#define SDRAM_tRP_num 1
83#define SDRAM_tRAS TRAS_3
84#define SDRAM_tRAS_num 3
85#define SDRAM_tRCD TRCD_1
86#define SDRAM_tWR TWR_2
87#endif
88#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
89#define SDRAM_tRP TRP_1
90#define SDRAM_tRP_num 1
91#define SDRAM_tRAS TRAS_2
92#define SDRAM_tRAS_num 2
93#define SDRAM_tRCD TRCD_1
94#define SDRAM_tWR TWR_2
95#endif
96#if (CONFIG_SCLK_HZ <= 29850746)
97#define SDRAM_tRP TRP_1
98#define SDRAM_tRP_num 1
99#define SDRAM_tRAS TRAS_1
100#define SDRAM_tRAS_num 1
101#define SDRAM_tRCD TRCD_1
102#define SDRAM_tWR TWR_2
103#endif
104#endif
105
106#if (CONFIG_MEM_MT48LC16M16A2TG_75)
107 /*SDRAM INFORMATION: */
108#define SDRAM_Tref 64 /* Refresh period in milliseconds */
109#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
110#define SDRAM_CL CL_3
111#endif
112
113#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114 /*SDRAM INFORMATION: */
115#define SDRAM_Tref 64 /* Refresh period in milliseconds */
116#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
117#define SDRAM_CL CL_3
118#endif
119
120#if (CONFIG_MEM_MT48LC8M32B2B5_7)
121 /*SDRAM INFORMATION: */
122#define SDRAM_Tref 64 /* Refresh period in milliseconds */
123#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124#define SDRAM_CL CL_3
125#endif
126
127#if (CONFIG_MEM_GENERIC_BOARD)
128 /*SDRAM INFORMATION: Modify this for your board */
129#define SDRAM_Tref 64 /* Refresh period in milliseconds */
130#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
131#define SDRAM_CL CL_3
132#endif
133
134/* Equation from section 17 (p17-46) of BF533 HRM */
135#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
136
137/* Enable SCLK Out */
138#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
139
140#if defined CONFIG_CLKIN_HALF
141#define CLKIN_HALF 1
142#else
143#define CLKIN_HALF 0
144#endif
145
146#if defined CONFIG_PLL_BYPASS
147#define PLL_BYPASS 1
148#else
149#define PLL_BYPASS 0
150#endif
151
152/***************************************Currently Not Being Used *********************************/
153#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
154#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
155#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
156#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
158
159#if (flash_EBIU_AMBCTL_TT > 3)
160#define flash_EBIU_AMBCTL0_TT B0TT_4
161#endif
162#if (flash_EBIU_AMBCTL_TT == 3)
163#define flash_EBIU_AMBCTL0_TT B0TT_3
164#endif
165#if (flash_EBIU_AMBCTL_TT == 2)
166#define flash_EBIU_AMBCTL0_TT B0TT_2
167#endif
168#if (flash_EBIU_AMBCTL_TT < 2)
169#define flash_EBIU_AMBCTL0_TT B0TT_1
170#endif
171
172#if (flash_EBIU_AMBCTL_ST > 3)
173#define flash_EBIU_AMBCTL0_ST B0ST_4
174#endif
175#if (flash_EBIU_AMBCTL_ST == 3)
176#define flash_EBIU_AMBCTL0_ST B0ST_3
177#endif
178#if (flash_EBIU_AMBCTL_ST == 2)
179#define flash_EBIU_AMBCTL0_ST B0ST_2
180#endif
181#if (flash_EBIU_AMBCTL_ST < 2)
182#define flash_EBIU_AMBCTL0_ST B0ST_1
183#endif
184
185#if (flash_EBIU_AMBCTL_HT > 2)
186#define flash_EBIU_AMBCTL0_HT B0HT_3
187#endif
188#if (flash_EBIU_AMBCTL_HT == 2)
189#define flash_EBIU_AMBCTL0_HT B0HT_2
190#endif
191#if (flash_EBIU_AMBCTL_HT == 1)
192#define flash_EBIU_AMBCTL0_HT B0HT_1
193#endif
194#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
195#define flash_EBIU_AMBCTL0_HT B0HT_0
196#endif
197#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
198#define flash_EBIU_AMBCTL0_HT B0HT_1
199#endif
200
201#if (flash_EBIU_AMBCTL_WAT > 14)
202#define flash_EBIU_AMBCTL0_WAT B0WAT_15
203#endif
204#if (flash_EBIU_AMBCTL_WAT == 14)
205#define flash_EBIU_AMBCTL0_WAT B0WAT_14
206#endif
207#if (flash_EBIU_AMBCTL_WAT == 13)
208#define flash_EBIU_AMBCTL0_WAT B0WAT_13
209#endif
210#if (flash_EBIU_AMBCTL_WAT == 12)
211#define flash_EBIU_AMBCTL0_WAT B0WAT_12
212#endif
213#if (flash_EBIU_AMBCTL_WAT == 11)
214#define flash_EBIU_AMBCTL0_WAT B0WAT_11
215#endif
216#if (flash_EBIU_AMBCTL_WAT == 10)
217#define flash_EBIU_AMBCTL0_WAT B0WAT_10
218#endif
219#if (flash_EBIU_AMBCTL_WAT == 9)
220#define flash_EBIU_AMBCTL0_WAT B0WAT_9
221#endif
222#if (flash_EBIU_AMBCTL_WAT == 8)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_8
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 7)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_7
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 6)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_6
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 5)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_5
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 4)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_4
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 3)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_3
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 2)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_2
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 1)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_1
245#endif
246
247#if (flash_EBIU_AMBCTL_RAT > 14)
248#define flash_EBIU_AMBCTL0_RAT B0RAT_15
249#endif
250#if (flash_EBIU_AMBCTL_RAT == 14)
251#define flash_EBIU_AMBCTL0_RAT B0RAT_14
252#endif
253#if (flash_EBIU_AMBCTL_RAT == 13)
254#define flash_EBIU_AMBCTL0_RAT B0RAT_13
255#endif
256#if (flash_EBIU_AMBCTL_RAT == 12)
257#define flash_EBIU_AMBCTL0_RAT B0RAT_12
258#endif
259#if (flash_EBIU_AMBCTL_RAT == 11)
260#define flash_EBIU_AMBCTL0_RAT B0RAT_11
261#endif
262#if (flash_EBIU_AMBCTL_RAT == 10)
263#define flash_EBIU_AMBCTL0_RAT B0RAT_10
264#endif
265#if (flash_EBIU_AMBCTL_RAT == 9)
266#define flash_EBIU_AMBCTL0_RAT B0RAT_9
267#endif
268#if (flash_EBIU_AMBCTL_RAT == 8)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_8
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 7)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_7
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 6)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_6
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 5)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_5
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 4)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_4
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 3)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_3
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 2)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_2
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 1)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_1
291#endif
292
293#define flash_EBIU_AMBCTL0 \
294 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
295 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
new file mode 100644
index 000000000000..c26d8486cc4b
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -0,0 +1,78 @@
1/*
2 * Memory MAP
3 * Common header file for blackfin BF561 of processors.
4 */
5
6#ifndef _MEM_MAP_561_H_
7#define _MEM_MAP_561_H_
8
9#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
10#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
11
12/* Async Memory Banks */
13#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
14#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
15#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
16#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
17#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
18#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
19#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
20#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
21
22/* Boot ROM Memory */
23
24#define BOOT_ROM_START 0xEF000000
25#define BOOT_ROM_LENGTH 0x800
26
27/* Level 1 Memory */
28
29#ifdef CONFIG_BFIN_ICACHE
30#define BFIN_ICACHESIZE (16*1024)
31#else
32#define BFIN_ICACHESIZE (0*1024)
33#endif
34
35/* Memory Map for ADSP-BF561 processors */
36
37#ifdef CONFIG_BF561
38#define L1_CODE_START 0xFFA00000
39#define L1_DATA_A_START 0xFF800000
40#define L1_DATA_B_START 0xFF900000
41
42#define L1_CODE_LENGTH 0x4000
43
44#ifdef CONFIG_BFIN_DCACHE
45
46#ifdef CONFIG_BFIN_DCACHE_BANKA
47#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
48#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
49#define L1_DATA_B_LENGTH 0x8000
50#define BFIN_DCACHESIZE (16*1024)
51#define BFIN_DSUPBANKS 1
52#else
53#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
54#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
55#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
56#define BFIN_DCACHESIZE (32*1024)
57#define BFIN_DSUPBANKS 2
58#endif
59
60#else
61#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
62#define L1_DATA_A_LENGTH 0x8000
63#define L1_DATA_B_LENGTH 0x8000
64#define BFIN_DCACHESIZE (0*1024)
65#define BFIN_DSUPBANKS 0
66#endif /*CONFIG_BFIN_DCACHE*/
67#endif
68
69/* Level 2 Memory */
70#define L2_START 0xFEB00000
71#define L2_LENGTH 0x20000
72
73/* Scratch Pad Memory */
74
75#define L1_SCRATCH_START 0xFFB00000
76#define L1_SCRATCH_LENGTH 0x1000
77
78#endif /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/portmux.h b/arch/blackfin/mach-bf561/include/mach/portmux.h
new file mode 100644
index 000000000000..a6ee8206efb6
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/portmux.h
@@ -0,0 +1,89 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
6#define P_PPI0_CLK (P_DONTCARE)
7#define P_PPI0_FS1 (P_DONTCARE)
8#define P_PPI0_FS2 (P_DONTCARE)
9#define P_PPI0_FS3 (P_DONTCARE)
10#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
11#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
12#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
13#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
14#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
15#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
16#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
17#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
18#define P_PPI0_D0 (P_DONTCARE)
19#define P_PPI0_D1 (P_DONTCARE)
20#define P_PPI0_D2 (P_DONTCARE)
21#define P_PPI0_D3 (P_DONTCARE)
22#define P_PPI0_D4 (P_DONTCARE)
23#define P_PPI0_D5 (P_DONTCARE)
24#define P_PPI0_D6 (P_DONTCARE)
25#define P_PPI0_D7 (P_DONTCARE)
26#define P_PPI1_CLK (P_DONTCARE)
27#define P_PPI1_FS1 (P_DONTCARE)
28#define P_PPI1_FS2 (P_DONTCARE)
29#define P_PPI1_FS3 (P_DONTCARE)
30#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
31#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
32#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
33#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
34#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
35#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
36#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
37#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
38#define P_PPI1_D0 (P_DONTCARE)
39#define P_PPI1_D1 (P_DONTCARE)
40#define P_PPI1_D2 (P_DONTCARE)
41#define P_PPI1_D3 (P_DONTCARE)
42#define P_PPI1_D4 (P_DONTCARE)
43#define P_PPI1_D5 (P_DONTCARE)
44#define P_PPI1_D6 (P_DONTCARE)
45#define P_PPI1_D7 (P_DONTCARE)
46#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
47#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
48#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
49#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
50#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
51#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
52#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
53#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
54#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
55#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
56#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
57#define P_SPORT1_DRPRI (P_DONTCARE)
58#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
59#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
60#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
61#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
62#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
63#define P_SPORT0_DRPRI (P_DONTCARE)
64#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
65#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
66#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
67#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
68#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
69#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
70#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
71#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
72#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
73#define P_TMR11 (P_DONTCARE)
74#define P_TMR10 (P_DONTCARE)
75#define P_TMR9 (P_DONTCARE)
76#define P_TMR8 (P_DONTCARE)
77#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
78#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
79#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
80#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
81#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
82#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
83#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
84#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
85#define P_SPI0_MOSI (P_DONTCARE)
86#define P_SPI0_MISO (P_DONTCARE)
87#define P_SPI0_SCK (P_DONTCARE)
88
89#endif /* _MACH_PORTMUX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-03 09:29:48 -0400