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-rw-r--r--arch/blackfin/mach-bf561/Kconfig8
-rw-r--r--arch/blackfin/mach-bf561/Makefile3
-rw-r--r--arch/blackfin/mach-bf561/atomic.S919
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c39
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c89
-rw-r--r--arch/blackfin/mach-bf561/boards/generic_board.c35
-rw-r--r--arch/blackfin/mach-bf561/boards/tepla.c34
-rw-r--r--arch/blackfin/mach-bf561/dma.c2
-rw-r--r--arch/blackfin/mach-bf561/head.S136
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h16
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bf561.h2
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_sir.h125
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h4
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h103
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h3
-rw-r--r--arch/blackfin/mach-bf561/include/mach/dma.h16
-rw-r--r--arch/blackfin/mach-bf561/include/mach/gpio.h68
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_init.h295
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h80
-rw-r--r--arch/blackfin/mach-bf561/include/mach/smp.h22
-rw-r--r--arch/blackfin/mach-bf561/secondary.S215
-rw-r--r--arch/blackfin/mach-bf561/smp.c167
22 files changed, 1712 insertions, 669 deletions
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
index 3f4895450bea..638ec38ca470 100644
--- a/arch/blackfin/mach-bf561/Kconfig
+++ b/arch/blackfin/mach-bf561/Kconfig
@@ -4,9 +4,9 @@ source "arch/blackfin/mach-bf561/boards/Kconfig"
4 4
5menu "BF561 Specific Configuration" 5menu "BF561 Specific Configuration"
6 6
7comment "Core B Support" 7if (!SMP)
8 8
9menu "Core B Support" 9comment "Core B Support"
10 10
11config BF561_COREB 11config BF561_COREB
12 bool "Enable Core B support" 12 bool "Enable Core B support"
@@ -25,7 +25,7 @@ config BF561_COREB_RESET
25 0 is set, and will reset PC to 0xff600000 when 25 0 is set, and will reset PC to 0xff600000 when
26 COREB_SRAM_INIT is cleared. 26 COREB_SRAM_INIT is cleared.
27 27
28endmenu 28endif
29 29
30comment "Interrupt Priority Assignment" 30comment "Interrupt Priority Assignment"
31 31
@@ -138,7 +138,7 @@ config IRQ_DMA2_11
138 default 9 138 default 9
139config IRQ_TIMER0 139config IRQ_TIMER0
140 int "TIMER 0 Interrupt" 140 int "TIMER 0 Interrupt"
141 default 10 141 default 8
142config IRQ_TIMER1 142config IRQ_TIMER1
143 int "TIMER 1 Interrupt" 143 int "TIMER 1 Interrupt"
144 default 10 144 default 10
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
index f39235a55783..59e18afe28c6 100644
--- a/arch/blackfin/mach-bf561/Makefile
+++ b/arch/blackfin/mach-bf561/Makefile
@@ -2,8 +2,7 @@
2# arch/blackfin/mach-bf561/Makefile 2# arch/blackfin/mach-bf561/Makefile
3# 3#
4 4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o 5obj-y := ints-priority.o dma.o
8 6
9obj-$(CONFIG_BF561_COREB) += coreb.o 7obj-$(CONFIG_BF561_COREB) += coreb.o
8obj-$(CONFIG_SMP) += smp.o secondary.o atomic.o
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
new file mode 100644
index 000000000000..9439bc6bd01f
--- /dev/null
+++ b/arch/blackfin/mach-bf561/atomic.S
@@ -0,0 +1,919 @@
1/*
2 * File: arch/blackfin/mach-bf561/atomic.S
3 * Author: Philippe Gerum <rpm@xenomai.org>
4 *
5 * Copyright 2007 Analog Devices Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see the file COPYING, or write
19 * to the Free Software Foundation, Inc.,
20 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <linux/linkage.h>
24#include <asm/blackfin.h>
25#include <asm/cache.h>
26#include <asm/asm-offsets.h>
27#include <asm/rwlock.h>
28#include <asm/cplb.h>
29
30.text
31
32.macro coreslot_loadaddr reg:req
33 \reg\().l = _corelock;
34 \reg\().h = _corelock;
35.endm
36
37/*
38 * r0 = address of atomic data to flush and invalidate (32bit).
39 *
40 * Clear interrupts and return the old mask.
41 * We assume that no atomic data can span cachelines.
42 *
43 * Clobbers: r2:0, p0
44 */
45ENTRY(_get_core_lock)
46 r1 = -L1_CACHE_BYTES;
47 r1 = r0 & r1;
48 cli r0;
49 coreslot_loadaddr p0;
50.Lretry_corelock:
51 testset (p0);
52 if cc jump .Ldone_corelock;
53 SSYNC(r2);
54 jump .Lretry_corelock
55.Ldone_corelock:
56 p0 = r1;
57 CSYNC(r2);
58 flushinv[p0];
59 SSYNC(r2);
60 rts;
61ENDPROC(_get_core_lock)
62
63/*
64 * r0 = address of atomic data in uncacheable memory region (32bit).
65 *
66 * Clear interrupts and return the old mask.
67 *
68 * Clobbers: r0, p0
69 */
70ENTRY(_get_core_lock_noflush)
71 cli r0;
72 coreslot_loadaddr p0;
73.Lretry_corelock_noflush:
74 testset (p0);
75 if cc jump .Ldone_corelock_noflush;
76 SSYNC(r2);
77 jump .Lretry_corelock_noflush
78.Ldone_corelock_noflush:
79 rts;
80ENDPROC(_get_core_lock_noflush)
81
82/*
83 * r0 = interrupt mask to restore.
84 * r1 = address of atomic data to flush and invalidate (32bit).
85 *
86 * Interrupts are masked on entry (see _get_core_lock).
87 * Clobbers: r2:0, p0
88 */
89ENTRY(_put_core_lock)
90 /* Write-through cache assumed, so no flush needed here. */
91 coreslot_loadaddr p0;
92 r1 = 0;
93 [p0] = r1;
94 SSYNC(r2);
95 sti r0;
96 rts;
97ENDPROC(_put_core_lock)
98
99#ifdef __ARCH_SYNC_CORE_DCACHE
100
101ENTRY(___raw_smp_mark_barrier_asm)
102 [--sp] = rets;
103 [--sp] = ( r7:5 );
104 [--sp] = r0;
105 [--sp] = p1;
106 [--sp] = p0;
107 call _get_core_lock_noflush;
108
109 /*
110 * Calculate current core mask
111 */
112 GET_CPUID(p1, r7);
113 r6 = 1;
114 r6 <<= r7;
115
116 /*
117 * Set bit of other cores in barrier mask. Don't change current core bit.
118 */
119 p1.l = _barrier_mask;
120 p1.h = _barrier_mask;
121 r7 = [p1];
122 r5 = r7 & r6;
123 r7 = ~r6;
124 cc = r5 == 0;
125 if cc jump 1f;
126 r7 = r7 | r6;
1271:
128 [p1] = r7;
129 SSYNC(r2);
130
131 call _put_core_lock;
132 p0 = [sp++];
133 p1 = [sp++];
134 r0 = [sp++];
135 ( r7:5 ) = [sp++];
136 rets = [sp++];
137 rts;
138ENDPROC(___raw_smp_mark_barrier_asm)
139
140ENTRY(___raw_smp_check_barrier_asm)
141 [--sp] = rets;
142 [--sp] = ( r7:5 );
143 [--sp] = r0;
144 [--sp] = p1;
145 [--sp] = p0;
146 call _get_core_lock_noflush;
147
148 /*
149 * Calculate current core mask
150 */
151 GET_CPUID(p1, r7);
152 r6 = 1;
153 r6 <<= r7;
154
155 /*
156 * Clear current core bit in barrier mask if it is set.
157 */
158 p1.l = _barrier_mask;
159 p1.h = _barrier_mask;
160 r7 = [p1];
161 r5 = r7 & r6;
162 cc = r5 == 0;
163 if cc jump 1f;
164 r6 = ~r6;
165 r7 = r7 & r6;
166 [p1] = r7;
167 SSYNC(r2);
168
169 call _put_core_lock;
170
171 /*
172 * Invalidate the entire D-cache of current core.
173 */
174 sp += -12;
175 call _resync_core_dcache
176 sp += 12;
177 jump 2f;
1781:
179 call _put_core_lock;
1802:
181 p0 = [sp++];
182 p1 = [sp++];
183 r0 = [sp++];
184 ( r7:5 ) = [sp++];
185 rets = [sp++];
186 rts;
187ENDPROC(___raw_smp_check_barrier_asm)
188
189/*
190 * r0 = irqflags
191 * r1 = address of atomic data
192 *
193 * Clobbers: r2:0, p1:0
194 */
195_start_lock_coherent:
196
197 [--sp] = rets;
198 [--sp] = ( r7:6 );
199 r7 = r0;
200 p1 = r1;
201
202 /*
203 * Determine whether the atomic data was previously
204 * owned by another CPU (=r6).
205 */
206 GET_CPUID(p0, r2);
207 r1 = 1;
208 r1 <<= r2;
209 r2 = ~r1;
210
211 r1 = [p1];
212 r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */
213 r6 = r1 & r2;
214 r1 = [p1];
215 r1 <<= 4;
216 r1 >>= 4;
217 [p1] = r1;
218
219 /*
220 * Release the core lock now, but keep IRQs disabled while we are
221 * performing the remaining housekeeping chores for the current CPU.
222 */
223 coreslot_loadaddr p0;
224 r1 = 0;
225 [p0] = r1;
226
227 /*
228 * If another CPU has owned the same atomic section before us,
229 * then our D-cached copy of the shared data protected by the
230 * current spin/write_lock may be obsolete.
231 */
232 cc = r6 == 0;
233 if cc jump .Lcache_synced
234
235 /*
236 * Invalidate the entire D-cache of the current core.
237 */
238 sp += -12;
239 call _resync_core_dcache
240 sp += 12;
241
242.Lcache_synced:
243 SSYNC(r2);
244 sti r7;
245 ( r7:6 ) = [sp++];
246 rets = [sp++];
247 rts
248
249/*
250 * r0 = irqflags
251 * r1 = address of atomic data
252 *
253 * Clobbers: r2:0, p1:0
254 */
255_end_lock_coherent:
256
257 p1 = r1;
258 GET_CPUID(p0, r2);
259 r2 += 28;
260 r1 = 1;
261 r1 <<= r2;
262 r2 = [p1];
263 r2 = r1 | r2;
264 [p1] = r2;
265 r1 = p1;
266 jump _put_core_lock;
267
268#endif /* __ARCH_SYNC_CORE_DCACHE */
269
270/*
271 * r0 = &spinlock->lock
272 *
273 * Clobbers: r3:0, p1:0
274 */
275ENTRY(___raw_spin_is_locked_asm)
276 p1 = r0;
277 [--sp] = rets;
278 call _get_core_lock;
279 r3 = [p1];
280 cc = bittst( r3, 0 );
281 r3 = cc;
282 r1 = p1;
283 call _put_core_lock;
284 rets = [sp++];
285 r0 = r3;
286 rts;
287ENDPROC(___raw_spin_is_locked_asm)
288
289/*
290 * r0 = &spinlock->lock
291 *
292 * Clobbers: r3:0, p1:0
293 */
294ENTRY(___raw_spin_lock_asm)
295 p1 = r0;
296 [--sp] = rets;
297.Lretry_spinlock:
298 call _get_core_lock;
299 r1 = p1;
300 r2 = [p1];
301 cc = bittst( r2, 0 );
302 if cc jump .Lbusy_spinlock
303#ifdef __ARCH_SYNC_CORE_DCACHE
304 r3 = p1;
305 bitset ( r2, 0 ); /* Raise the lock bit. */
306 [p1] = r2;
307 call _start_lock_coherent
308#else
309 r2 = 1;
310 [p1] = r2;
311 call _put_core_lock;
312#endif
313 rets = [sp++];
314 rts;
315
316.Lbusy_spinlock:
317 /* We don't touch the atomic area if busy, so that flush
318 will behave like nop in _put_core_lock. */
319 call _put_core_lock;
320 SSYNC(r2);
321 r0 = p1;
322 jump .Lretry_spinlock
323ENDPROC(___raw_spin_lock_asm)
324
325/*
326 * r0 = &spinlock->lock
327 *
328 * Clobbers: r3:0, p1:0
329 */
330ENTRY(___raw_spin_trylock_asm)
331 p1 = r0;
332 [--sp] = rets;
333 call _get_core_lock;
334 r1 = p1;
335 r3 = [p1];
336 cc = bittst( r3, 0 );
337 if cc jump .Lfailed_trylock
338#ifdef __ARCH_SYNC_CORE_DCACHE
339 bitset ( r3, 0 ); /* Raise the lock bit. */
340 [p1] = r3;
341 call _start_lock_coherent
342#else
343 r2 = 1;
344 [p1] = r2;
345 call _put_core_lock;
346#endif
347 r0 = 1;
348 rets = [sp++];
349 rts;
350.Lfailed_trylock:
351 call _put_core_lock;
352 r0 = 0;
353 rets = [sp++];
354 rts;
355ENDPROC(___raw_spin_trylock_asm)
356
357/*
358 * r0 = &spinlock->lock
359 *
360 * Clobbers: r2:0, p1:0
361 */
362ENTRY(___raw_spin_unlock_asm)
363 p1 = r0;
364 [--sp] = rets;
365 call _get_core_lock;
366 r2 = [p1];
367 bitclr ( r2, 0 );
368 [p1] = r2;
369 r1 = p1;
370#ifdef __ARCH_SYNC_CORE_DCACHE
371 call _end_lock_coherent
372#else
373 call _put_core_lock;
374#endif
375 rets = [sp++];
376 rts;
377ENDPROC(___raw_spin_unlock_asm)
378
379/*
380 * r0 = &rwlock->lock
381 *
382 * Clobbers: r2:0, p1:0
383 */
384ENTRY(___raw_read_lock_asm)
385 p1 = r0;
386 [--sp] = rets;
387 call _get_core_lock;
388.Lrdlock_try:
389 r1 = [p1];
390 r1 += -1;
391 [p1] = r1;
392 cc = r1 < 0;
393 if cc jump .Lrdlock_failed
394 r1 = p1;
395#ifdef __ARCH_SYNC_CORE_DCACHE
396 call _start_lock_coherent
397#else
398 call _put_core_lock;
399#endif
400 rets = [sp++];
401 rts;
402
403.Lrdlock_failed:
404 r1 += 1;
405 [p1] = r1;
406.Lrdlock_wait:
407 r1 = p1;
408 call _put_core_lock;
409 SSYNC(r2);
410 r0 = p1;
411 call _get_core_lock;
412 r1 = [p1];
413 cc = r1 < 2;
414 if cc jump .Lrdlock_wait;
415 jump .Lrdlock_try
416ENDPROC(___raw_read_lock_asm)
417
418/*
419 * r0 = &rwlock->lock
420 *
421 * Clobbers: r3:0, p1:0
422 */
423ENTRY(___raw_read_trylock_asm)
424 p1 = r0;
425 [--sp] = rets;
426 call _get_core_lock;
427 r1 = [p1];
428 cc = r1 <= 0;
429 if cc jump .Lfailed_tryrdlock;
430 r1 += -1;
431 [p1] = r1;
432 r1 = p1;
433#ifdef __ARCH_SYNC_CORE_DCACHE
434 call _start_lock_coherent
435#else
436 call _put_core_lock;
437#endif
438 rets = [sp++];
439 r0 = 1;
440 rts;
441.Lfailed_tryrdlock:
442 r1 = p1;
443 call _put_core_lock;
444 rets = [sp++];
445 r0 = 0;
446 rts;
447ENDPROC(___raw_read_trylock_asm)
448
449/*
450 * r0 = &rwlock->lock
451 *
452 * Note: Processing controlled by a reader lock should not have
453 * any side-effect on cache issues with the other core, so we
454 * just release the core lock and exit (no _end_lock_coherent).
455 *
456 * Clobbers: r3:0, p1:0
457 */
458ENTRY(___raw_read_unlock_asm)
459 p1 = r0;
460 [--sp] = rets;
461 call _get_core_lock;
462 r1 = [p1];
463 r1 += 1;
464 [p1] = r1;
465 r1 = p1;
466 call _put_core_lock;
467 rets = [sp++];
468 rts;
469ENDPROC(___raw_read_unlock_asm)
470
471/*
472 * r0 = &rwlock->lock
473 *
474 * Clobbers: r3:0, p1:0
475 */
476ENTRY(___raw_write_lock_asm)
477 p1 = r0;
478 r3.l = lo(RW_LOCK_BIAS);
479 r3.h = hi(RW_LOCK_BIAS);
480 [--sp] = rets;
481 call _get_core_lock;
482.Lwrlock_try:
483 r1 = [p1];
484 r1 = r1 - r3;
485#ifdef __ARCH_SYNC_CORE_DCACHE
486 r2 = r1;
487 r2 <<= 4;
488 r2 >>= 4;
489 cc = r2 == 0;
490#else
491 cc = r1 == 0;
492#endif
493 if !cc jump .Lwrlock_wait
494 [p1] = r1;
495 r1 = p1;
496#ifdef __ARCH_SYNC_CORE_DCACHE
497 call _start_lock_coherent
498#else
499 call _put_core_lock;
500#endif
501 rets = [sp++];
502 rts;
503
504.Lwrlock_wait:
505 r1 = p1;
506 call _put_core_lock;
507 SSYNC(r2);
508 r0 = p1;
509 call _get_core_lock;
510 r1 = [p1];
511#ifdef __ARCH_SYNC_CORE_DCACHE
512 r1 <<= 4;
513 r1 >>= 4;
514#endif
515 cc = r1 == r3;
516 if !cc jump .Lwrlock_wait;
517 jump .Lwrlock_try
518ENDPROC(___raw_write_lock_asm)
519
520/*
521 * r0 = &rwlock->lock
522 *
523 * Clobbers: r3:0, p1:0
524 */
525ENTRY(___raw_write_trylock_asm)
526 p1 = r0;
527 [--sp] = rets;
528 call _get_core_lock;
529 r1 = [p1];
530 r2.l = lo(RW_LOCK_BIAS);
531 r2.h = hi(RW_LOCK_BIAS);
532 cc = r1 == r2;
533 if !cc jump .Lfailed_trywrlock;
534#ifdef __ARCH_SYNC_CORE_DCACHE
535 r1 >>= 28;
536 r1 <<= 28;
537#else
538 r1 = 0;
539#endif
540 [p1] = r1;
541 r1 = p1;
542#ifdef __ARCH_SYNC_CORE_DCACHE
543 call _start_lock_coherent
544#else
545 call _put_core_lock;
546#endif
547 rets = [sp++];
548 r0 = 1;
549 rts;
550
551.Lfailed_trywrlock:
552 r1 = p1;
553 call _put_core_lock;
554 rets = [sp++];
555 r0 = 0;
556 rts;
557ENDPROC(___raw_write_trylock_asm)
558
559/*
560 * r0 = &rwlock->lock
561 *
562 * Clobbers: r3:0, p1:0
563 */
564ENTRY(___raw_write_unlock_asm)
565 p1 = r0;
566 r3.l = lo(RW_LOCK_BIAS);
567 r3.h = hi(RW_LOCK_BIAS);
568 [--sp] = rets;
569 call _get_core_lock;
570 r1 = [p1];
571 r1 = r1 + r3;
572 [p1] = r1;
573 r1 = p1;
574#ifdef __ARCH_SYNC_CORE_DCACHE
575 call _end_lock_coherent
576#else
577 call _put_core_lock;
578#endif
579 rets = [sp++];
580 rts;
581ENDPROC(___raw_write_unlock_asm)
582
583/*
584 * r0 = ptr
585 * r1 = value
586 *
587 * Add a signed value to a 32bit word and return the new value atomically.
588 * Clobbers: r3:0, p1:0
589 */
590ENTRY(___raw_atomic_update_asm)
591 p1 = r0;
592 r3 = r1;
593 [--sp] = rets;
594 call _get_core_lock;
595 r2 = [p1];
596 r3 = r3 + r2;
597 [p1] = r3;
598 r1 = p1;
599 call _put_core_lock;
600 r0 = r3;
601 rets = [sp++];
602 rts;
603ENDPROC(___raw_atomic_update_asm)
604
605/*
606 * r0 = ptr
607 * r1 = mask
608 *
609 * Clear the mask bits from a 32bit word and return the old 32bit value
610 * atomically.
611 * Clobbers: r3:0, p1:0
612 */
613ENTRY(___raw_atomic_clear_asm)
614 p1 = r0;
615 r3 = ~r1;
616 [--sp] = rets;
617 call _get_core_lock;
618 r2 = [p1];
619 r3 = r2 & r3;
620 [p1] = r3;
621 r3 = r2;
622 r1 = p1;
623 call _put_core_lock;
624 r0 = r3;
625 rets = [sp++];
626 rts;
627ENDPROC(___raw_atomic_clear_asm)
628
629/*
630 * r0 = ptr
631 * r1 = mask
632 *
633 * Set the mask bits into a 32bit word and return the old 32bit value
634 * atomically.
635 * Clobbers: r3:0, p1:0
636 */
637ENTRY(___raw_atomic_set_asm)
638 p1 = r0;
639 r3 = r1;
640 [--sp] = rets;
641 call _get_core_lock;
642 r2 = [p1];
643 r3 = r2 | r3;
644 [p1] = r3;
645 r3 = r2;
646 r1 = p1;
647 call _put_core_lock;
648 r0 = r3;
649 rets = [sp++];
650 rts;
651ENDPROC(___raw_atomic_set_asm)
652
653/*
654 * r0 = ptr
655 * r1 = mask
656 *
657 * XOR the mask bits with a 32bit word and return the old 32bit value
658 * atomically.
659 * Clobbers: r3:0, p1:0
660 */
661ENTRY(___raw_atomic_xor_asm)
662 p1 = r0;
663 r3 = r1;
664 [--sp] = rets;
665 call _get_core_lock;
666 r2 = [p1];
667 r3 = r2 ^ r3;
668 [p1] = r3;
669 r3 = r2;
670 r1 = p1;
671 call _put_core_lock;
672 r0 = r3;
673 rets = [sp++];
674 rts;
675ENDPROC(___raw_atomic_xor_asm)
676
677/*
678 * r0 = ptr
679 * r1 = mask
680 *
681 * Perform a logical AND between the mask bits and a 32bit word, and
682 * return the masked value. We need this on this architecture in
683 * order to invalidate the local cache before testing.
684 *
685 * Clobbers: r3:0, p1:0
686 */
687ENTRY(___raw_atomic_test_asm)
688 p1 = r0;
689 r3 = r1;
690 r1 = -L1_CACHE_BYTES;
691 r1 = r0 & r1;
692 p0 = r1;
693 flushinv[p0];
694 SSYNC(r2);
695 r0 = [p1];
696 r0 = r0 & r3;
697 rts;
698ENDPROC(___raw_atomic_test_asm)
699
700/*
701 * r0 = ptr
702 * r1 = value
703 *
704 * Swap *ptr with value and return the old 32bit value atomically.
705 * Clobbers: r3:0, p1:0
706 */
707#define __do_xchg(src, dst) \
708 p1 = r0; \
709 r3 = r1; \
710 [--sp] = rets; \
711 call _get_core_lock; \
712 r2 = src; \
713 dst = r3; \
714 r3 = r2; \
715 r1 = p1; \
716 call _put_core_lock; \
717 r0 = r3; \
718 rets = [sp++]; \
719 rts;
720
721ENTRY(___raw_xchg_1_asm)
722 __do_xchg(b[p1] (z), b[p1])
723ENDPROC(___raw_xchg_1_asm)
724
725ENTRY(___raw_xchg_2_asm)
726 __do_xchg(w[p1] (z), w[p1])
727ENDPROC(___raw_xchg_2_asm)
728
729ENTRY(___raw_xchg_4_asm)
730 __do_xchg([p1], [p1])
731ENDPROC(___raw_xchg_4_asm)
732
733/*
734 * r0 = ptr
735 * r1 = new
736 * r2 = old
737 *
738 * Swap *ptr with new if *ptr == old and return the previous *ptr
739 * value atomically.
740 *
741 * Clobbers: r3:0, p1:0
742 */
743#define __do_cmpxchg(src, dst) \
744 [--sp] = rets; \
745 [--sp] = r4; \
746 p1 = r0; \
747 r3 = r1; \
748 r4 = r2; \
749 call _get_core_lock; \
750 r2 = src; \
751 cc = r2 == r4; \
752 if !cc jump 1f; \
753 dst = r3; \
754 1: r3 = r2; \
755 r1 = p1; \
756 call _put_core_lock; \
757 r0 = r3; \
758 r4 = [sp++]; \
759 rets = [sp++]; \
760 rts;
761
762ENTRY(___raw_cmpxchg_1_asm)
763 __do_cmpxchg(b[p1] (z), b[p1])
764ENDPROC(___raw_cmpxchg_1_asm)
765
766ENTRY(___raw_cmpxchg_2_asm)
767 __do_cmpxchg(w[p1] (z), w[p1])
768ENDPROC(___raw_cmpxchg_2_asm)
769
770ENTRY(___raw_cmpxchg_4_asm)
771 __do_cmpxchg([p1], [p1])
772ENDPROC(___raw_cmpxchg_4_asm)
773
774/*
775 * r0 = ptr
776 * r1 = bitnr
777 *
778 * Set a bit in a 32bit word and return the old 32bit value atomically.
779 * Clobbers: r3:0, p1:0
780 */
781ENTRY(___raw_bit_set_asm)
782 r2 = r1;
783 r1 = 1;
784 r1 <<= r2;
785 jump ___raw_atomic_set_asm
786ENDPROC(___raw_bit_set_asm)
787
788/*
789 * r0 = ptr
790 * r1 = bitnr
791 *
792 * Clear a bit in a 32bit word and return the old 32bit value atomically.
793 * Clobbers: r3:0, p1:0
794 */
795ENTRY(___raw_bit_clear_asm)
796 r2 = r1;
797 r1 = 1;
798 r1 <<= r2;
799 jump ___raw_atomic_clear_asm
800ENDPROC(___raw_bit_clear_asm)
801
802/*
803 * r0 = ptr
804 * r1 = bitnr
805 *
806 * Toggle a bit in a 32bit word and return the old 32bit value atomically.
807 * Clobbers: r3:0, p1:0
808 */
809ENTRY(___raw_bit_toggle_asm)
810 r2 = r1;
811 r1 = 1;
812 r1 <<= r2;
813 jump ___raw_atomic_xor_asm
814ENDPROC(___raw_bit_toggle_asm)
815
816/*
817 * r0 = ptr
818 * r1 = bitnr
819 *
820 * Test-and-set a bit in a 32bit word and return the old bit value atomically.
821 * Clobbers: r3:0, p1:0
822 */
823ENTRY(___raw_bit_test_set_asm)
824 [--sp] = rets;
825 [--sp] = r1;
826 call ___raw_bit_set_asm
827 r1 = [sp++];
828 r2 = 1;
829 r2 <<= r1;
830 r0 = r0 & r2;
831 cc = r0 == 0;
832 if cc jump 1f
833 r0 = 1;
8341:
835 rets = [sp++];
836 rts;
837ENDPROC(___raw_bit_test_set_asm)
838
839/*
840 * r0 = ptr
841 * r1 = bitnr
842 *
843 * Test-and-clear a bit in a 32bit word and return the old bit value atomically.
844 * Clobbers: r3:0, p1:0
845 */
846ENTRY(___raw_bit_test_clear_asm)
847 [--sp] = rets;
848 [--sp] = r1;
849 call ___raw_bit_clear_asm
850 r1 = [sp++];
851 r2 = 1;
852 r2 <<= r1;
853 r0 = r0 & r2;
854 cc = r0 == 0;
855 if cc jump 1f
856 r0 = 1;
8571:
858 rets = [sp++];
859 rts;
860ENDPROC(___raw_bit_test_clear_asm)
861
862/*
863 * r0 = ptr
864 * r1 = bitnr
865 *
866 * Test-and-toggle a bit in a 32bit word,
867 * and return the old bit value atomically.
868 * Clobbers: r3:0, p1:0
869 */
870ENTRY(___raw_bit_test_toggle_asm)
871 [--sp] = rets;
872 [--sp] = r1;
873 call ___raw_bit_toggle_asm
874 r1 = [sp++];
875 r2 = 1;
876 r2 <<= r1;
877 r0 = r0 & r2;
878 cc = r0 == 0;
879 if cc jump 1f
880 r0 = 1;
8811:
882 rets = [sp++];
883 rts;
884ENDPROC(___raw_bit_test_toggle_asm)
885
886/*
887 * r0 = ptr
888 * r1 = bitnr
889 *
890 * Test a bit in a 32bit word and return its value.
891 * We need this on this architecture in order to invalidate
892 * the local cache before testing.
893 *
894 * Clobbers: r3:0, p1:0
895 */
896ENTRY(___raw_bit_test_asm)
897 r2 = r1;
898 r1 = 1;
899 r1 <<= r2;
900 jump ___raw_atomic_test_asm
901ENDPROC(___raw_bit_test_asm)
902
903/*
904 * r0 = ptr
905 *
906 * Fetch and return an uncached 32bit value.
907 *
908 * Clobbers: r2:0, p1:0
909 */
910ENTRY(___raw_uncached_fetch_asm)
911 p1 = r0;
912 r1 = -L1_CACHE_BYTES;
913 r1 = r0 & r1;
914 p0 = r1;
915 flushinv[p0];
916 SSYNC(r2);
917 r0 = [p1];
918 rts;
919ENDPROC(___raw_uncached_fetch_asm)
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 8f40990eea2f..6880d1ebfe60 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -230,6 +230,19 @@ static struct platform_device smc91x_device = {
230}; 230};
231#endif 231#endif
232 232
233static struct resource bfin_gpios_resources = {
234 .start = 0,
235 .end = MAX_BLACKFIN_GPIOS - 1,
236 .flags = IORESOURCE_IRQ,
237};
238
239static struct platform_device bfin_gpios_device = {
240 .name = "simple-gpio",
241 .id = -1,
242 .num_resources = 1,
243 .resource = &bfin_gpios_resources,
244};
245
233#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 246#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
234static struct resource isp1362_hcd_resources[] = { 247static struct resource isp1362_hcd_resources[] = {
235 { 248 {
@@ -287,23 +300,33 @@ static struct platform_device bfin_uart_device = {
287#endif 300#endif
288 301
289#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 302#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
290static struct resource bfin_sir_resources[] = {
291#ifdef CONFIG_BFIN_SIR0 303#ifdef CONFIG_BFIN_SIR0
304static struct resource bfin_sir0_resources[] = {
292 { 305 {
293 .start = 0xFFC00400, 306 .start = 0xFFC00400,
294 .end = 0xFFC004FF, 307 .end = 0xFFC004FF,
295 .flags = IORESOURCE_MEM, 308 .flags = IORESOURCE_MEM,
296 }, 309 },
297#endif 310 {
311 .start = IRQ_UART0_RX,
312 .end = IRQ_UART0_RX+1,
313 .flags = IORESOURCE_IRQ,
314 },
315 {
316 .start = CH_UART0_RX,
317 .end = CH_UART0_RX+1,
318 .flags = IORESOURCE_DMA,
319 },
298}; 320};
299 321
300static struct platform_device bfin_sir_device = { 322static struct platform_device bfin_sir0_device = {
301 .name = "bfin_sir", 323 .name = "bfin_sir",
302 .id = 0, 324 .id = 0,
303 .num_resources = ARRAY_SIZE(bfin_sir_resources), 325 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
304 .resource = bfin_sir_resources, 326 .resource = bfin_sir0_resources,
305}; 327};
306#endif 328#endif
329#endif
307 330
308#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 331#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
309#define PATA_INT IRQ_PF46 332#define PATA_INT IRQ_PF46
@@ -382,7 +405,9 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
382#endif 405#endif
383 406
384#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 407#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
385 &bfin_sir_device, 408#ifdef CONFIG_BFIN_SIR0
409 &bfin_sir0_device,
410#endif
386#endif 411#endif
387 412
388#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 413#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -400,6 +425,8 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
400#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 425#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
401 &bfin_pata_device, 426 &bfin_pata_device,
402#endif 427#endif
428
429 &bfin_gpios_device,
403}; 430};
404 431
405static int __init cm_bf561_init(void) 432static int __init cm_bf561_init(void)
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 50b4cdceccfe..0e2178a1aec5 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -43,53 +43,42 @@
43/* 43/*
44 * Name the Board for the /proc/cpuinfo 44 * Name the Board for the /proc/cpuinfo
45 */ 45 */
46const char bfin_board_name[] = "ADDS-BF561-EZKIT"; 46const char bfin_board_name[] = "ADI BF561-EZKIT";
47
48#define ISP1761_BASE 0x2C0F0000
49#define ISP1761_IRQ IRQ_PF10
50 47
51#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) 48#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
52static struct resource bfin_isp1761_resources[] = { 49#include <linux/usb/isp1760.h>
53 { 50static struct resource bfin_isp1760_resources[] = {
54 .name = "isp1761-regs", 51 [0] = {
55 .start = ISP1761_BASE + 0x00000000, 52 .start = 0x2C0F0000,
56 .end = ISP1761_BASE + 0x000fffff, 53 .end = 0x203C0000 + 0xfffff,
57 .flags = IORESOURCE_MEM, 54 .flags = IORESOURCE_MEM,
58 }, 55 },
59 { 56 [1] = {
60 .start = ISP1761_IRQ, 57 .start = IRQ_PF10,
61 .end = ISP1761_IRQ, 58 .end = IRQ_PF10,
62 .flags = IORESOURCE_IRQ, 59 .flags = IORESOURCE_IRQ,
63 }, 60 },
64}; 61};
65 62
66static struct platform_device bfin_isp1761_device = { 63static struct isp1760_platform_data isp1760_priv = {
67 .name = "isp1761", 64 .is_isp1761 = 0,
68 .id = 0, 65 .port1_disable = 0,
69 .num_resources = ARRAY_SIZE(bfin_isp1761_resources), 66 .bus_width_16 = 1,
70 .resource = bfin_isp1761_resources, 67 .port1_otg = 0,
68 .analog_oc = 0,
69 .dack_polarity_high = 0,
70 .dreq_polarity_high = 0,
71}; 71};
72 72
73static struct platform_device *bfin_isp1761_devices[] = { 73static struct platform_device bfin_isp1760_device = {
74 &bfin_isp1761_device, 74 .name = "isp1760-hcd",
75 .id = 0,
76 .dev = {
77 .platform_data = &isp1760_priv,
78 },
79 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
80 .resource = bfin_isp1760_resources,
75}; 81};
76
77int __init bfin_isp1761_init(void)
78{
79 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
80
81 printk(KERN_INFO "%s(): registering device resources\n", __func__);
82 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
83
84 return platform_add_devices(bfin_isp1761_devices, num_devices);
85}
86
87void __exit bfin_isp1761_exit(void)
88{
89 platform_device_unregister(&bfin_isp1761_device);
90}
91
92arch_initcall(bfin_isp1761_init);
93#endif 82#endif
94 83
95#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 84#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -221,23 +210,33 @@ static struct platform_device bfin_uart_device = {
221#endif 210#endif
222 211
223#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 212#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
224static struct resource bfin_sir_resources[] = {
225#ifdef CONFIG_BFIN_SIR0 213#ifdef CONFIG_BFIN_SIR0
214static struct resource bfin_sir0_resources[] = {
226 { 215 {
227 .start = 0xFFC00400, 216 .start = 0xFFC00400,
228 .end = 0xFFC004FF, 217 .end = 0xFFC004FF,
229 .flags = IORESOURCE_MEM, 218 .flags = IORESOURCE_MEM,
230 }, 219 },
231#endif 220 {
221 .start = IRQ_UART0_RX,
222 .end = IRQ_UART0_RX+1,
223 .flags = IORESOURCE_IRQ,
224 },
225 {
226 .start = CH_UART0_RX,
227 .end = CH_UART0_RX+1,
228 .flags = IORESOURCE_DMA,
229 },
232}; 230};
233 231
234static struct platform_device bfin_sir_device = { 232static struct platform_device bfin_sir0_device = {
235 .name = "bfin_sir", 233 .name = "bfin_sir",
236 .id = 0, 234 .id = 0,
237 .num_resources = ARRAY_SIZE(bfin_sir_resources), 235 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
238 .resource = bfin_sir_resources, 236 .resource = bfin_sir0_resources,
239}; 237};
240#endif 238#endif
239#endif
241 240
242#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 241#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
243static struct mtd_partition ezkit_partitions[] = { 242static struct mtd_partition ezkit_partitions[] = {
@@ -449,6 +448,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
449 &net2272_bfin_device, 448 &net2272_bfin_device,
450#endif 449#endif
451 450
451#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
452 &bfin_isp1760_device,
453#endif
454
452#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 455#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
453 &bfin_spi0_device, 456 &bfin_spi0_device,
454#endif 457#endif
@@ -458,7 +461,9 @@ static struct platform_device *ezkit_devices[] __initdata = {
458#endif 461#endif
459 462
460#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 463#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
461 &bfin_sir_device, 464#ifdef CONFIG_BFIN_SIR0
465 &bfin_sir0_device,
466#endif
462#endif 467#endif
463 468
464#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 469#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
index 2faa0072d614..0ba366a0e696 100644
--- a/arch/blackfin/mach-bf561/boards/generic_board.c
+++ b/arch/blackfin/mach-bf561/boards/generic_board.c
@@ -62,10 +62,45 @@ static struct platform_device smc91x_device = {
62}; 62};
63#endif 63#endif
64 64
65#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
66#ifdef CONFIG_BFIN_SIR0
67static struct resource bfin_sir0_resources[] = {
68 {
69 .start = 0xFFC00400,
70 .end = 0xFFC004FF,
71 .flags = IORESOURCE_MEM,
72 },
73 {
74 .start = IRQ_UART0_RX,
75 .end = IRQ_UART0_RX+1,
76 .flags = IORESOURCE_IRQ,
77 },
78 {
79 .start = CH_UART0_RX,
80 .end = CH_UART0_RX+1,
81 .flags = IORESOURCE_DMA,
82 },
83};
84
85static struct platform_device bfin_sir0_device = {
86 .name = "bfin_sir",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
89 .resource = bfin_sir0_resources,
90};
91#endif
92#endif
93
65static struct platform_device *generic_board_devices[] __initdata = { 94static struct platform_device *generic_board_devices[] __initdata = {
66#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 95#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
67 &smc91x_device, 96 &smc91x_device,
68#endif 97#endif
98
99#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
100#ifdef CONFIG_BFIN_SIR0
101 &bfin_sir0_device,
102#endif
103#endif
69}; 104};
70 105
71static int __init generic_board_init(void) 106static int __init generic_board_init(void)
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index c9174b39f98d..6f77dbe952f5 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -44,8 +44,42 @@ static struct platform_device smc91x_device = {
44 .resource = smc91x_resources, 44 .resource = smc91x_resources,
45}; 45};
46 46
47#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
48#ifdef CONFIG_BFIN_SIR0
49static struct resource bfin_sir0_resources[] = {
50 {
51 .start = 0xFFC00400,
52 .end = 0xFFC004FF,
53 .flags = IORESOURCE_MEM,
54 },
55 {
56 .start = IRQ_UART0_RX,
57 .end = IRQ_UART0_RX+1,
58 .flags = IORESOURCE_IRQ,
59 },
60 {
61 .start = CH_UART0_RX,
62 .end = CH_UART0_RX+1,
63 .flags = IORESOURCE_DMA,
64 },
65};
66
67static struct platform_device bfin_sir0_device = {
68 .name = "bfin_sir",
69 .id = 0,
70 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
71 .resource = bfin_sir0_resources,
72};
73#endif
74#endif
75
47static struct platform_device *tepla_devices[] __initdata = { 76static struct platform_device *tepla_devices[] __initdata = {
48 &smc91x_device, 77 &smc91x_device,
78#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
79#ifdef CONFIG_BFIN_SIR0
80 &bfin_sir0_device,
81#endif
82#endif
49}; 83};
50 84
51static int __init tepla_init(void) 85static int __init tepla_init(void)
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
index 24415eb82698..42b0037afe61 100644
--- a/arch/blackfin/mach-bf561/dma.c
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -31,7 +31,7 @@
31#include <asm/blackfin.h> 31#include <asm/blackfin.h>
32#include <asm/dma.h> 32#include <asm/dma.h>
33 33
34struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { 34struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
35 (struct dma_register *) DMA1_0_NEXT_DESC_PTR, 35 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_1_NEXT_DESC_PTR, 36 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
37 (struct dma_register *) DMA1_2_NEXT_DESC_PTR, 37 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
deleted file mode 100644
index 31a777a9e699..000000000000
--- a/arch/blackfin/mach-bf561/head.S
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf561/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author:
5 *
6 * Created:
7 * Description: BF561 startup file
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/clocks.h>
35#include <mach/mem_init.h>
36#endif
37
38.section .l1.text
39#ifdef CONFIG_BFIN_KERNEL_CLOCK
40ENTRY(_start_dma_code)
41 p0.h = hi(SICA_IWR0);
42 p0.l = lo(SICA_IWR0);
43 r0.l = 0x1;
44 [p0] = r0;
45 SSYNC;
46
47 /*
48 * Set PLL_CTL
49 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
50 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
51 * - [7] = output delay (add 200ps of delay to mem signals)
52 * - [6] = input delay (add 200ps of input delay to mem signals)
53 * - [5] = PDWN : 1=All Clocks off
54 * - [3] = STOPCK : 1=Core Clock off
55 * - [1] = PLL_OFF : 1=Disable Power to PLL
56 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
57 * all other bits set to zero
58 */
59
60 p0.h = hi(PLL_LOCKCNT);
61 p0.l = lo(PLL_LOCKCNT);
62 r0 = 0x300(Z);
63 w[p0] = r0.l;
64 ssync;
65
66 P2.H = hi(EBIU_SDGCTL);
67 P2.L = lo(EBIU_SDGCTL);
68 R0 = [P2];
69 BITSET (R0, 24);
70 [P2] = R0;
71 SSYNC;
72
73 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
74 r0 = r0 << 9; /* Shift it over, */
75 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
76 r0 = r1 | r0;
77 r1 = PLL_BYPASS; /* Bypass the PLL? */
78 r1 = r1 << 8; /* Shift it over */
79 r0 = r1 | r0; /* add them all together */
80#ifdef ANOMALY_05000265
81 BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
82#endif
83
84 p0.h = hi(PLL_CTL);
85 p0.l = lo(PLL_CTL); /* Load the address */
86 cli r2; /* Disable interrupts */
87 ssync;
88 w[p0] = r0.l; /* Set the value */
89 idle; /* Wait for the PLL to stablize */
90 sti r2; /* Enable interrupts */
91
92.Lcheck_again:
93 p0.h = hi(PLL_STAT);
94 p0.l = lo(PLL_STAT);
95 R0 = W[P0](Z);
96 CC = BITTST(R0,5);
97 if ! CC jump .Lcheck_again;
98
99 /* Configure SCLK & CCLK Dividers */
100 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
101 p0.h = hi(PLL_DIV);
102 p0.l = lo(PLL_DIV);
103 w[p0] = r0.l;
104 ssync;
105
106 p0.l = lo(EBIU_SDRRC);
107 p0.h = hi(EBIU_SDRRC);
108 r0 = mem_SDRRC;
109 w[p0] = r0.l;
110 ssync;
111
112 P2.H = hi(EBIU_SDGCTL);
113 P2.L = lo(EBIU_SDGCTL);
114 R0 = [P2];
115 BITCLR (R0, 24);
116 p0.h = hi(EBIU_SDSTAT);
117 p0.l = lo(EBIU_SDSTAT);
118 r2.l = w[p0];
119 cc = bittst(r2,3);
120 if !cc jump .Lskip;
121 NOP;
122 BITSET (R0, 23);
123.Lskip:
124 [P2] = R0;
125 SSYNC;
126
127 R0.L = lo(mem_SDGCTL);
128 R0.H = hi(mem_SDGCTL);
129 R1 = [p2];
130 R1 = R1 | R0;
131 [P2] = R1;
132 SSYNC;
133
134 RTS;
135ENDPROC(_start_dma_code)
136#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 22990df04ae1..1a9e17562821 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List 10 * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -264,6 +264,18 @@
264#define ANOMALY_05000371 (1) 264#define ANOMALY_05000371 (1)
265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266#define ANOMALY_05000403 (1) 266#define ANOMALY_05000403 (1)
267/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
268#define ANOMALY_05000412 (1)
269/* Speculative Fetches Can Cause Undesired External FIFO Operations */
270#define ANOMALY_05000416 (1)
271/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
272#define ANOMALY_05000425 (1)
273/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
274#define ANOMALY_05000426 (1)
275/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
276#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
277/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
278#define ANOMALY_05000443 (1)
267 279
268/* Anomalies that don't exist on this proc */ 280/* Anomalies that don't exist on this proc */
269#define ANOMALY_05000158 (0) 281#define ANOMALY_05000158 (0)
@@ -272,5 +284,7 @@
272#define ANOMALY_05000311 (0) 284#define ANOMALY_05000311 (0)
273#define ANOMALY_05000353 (1) 285#define ANOMALY_05000353 (1)
274#define ANOMALY_05000386 (1) 286#define ANOMALY_05000386 (1)
287#define ANOMALY_05000432 (0)
288#define ANOMALY_05000435 (0)
275 289
276#endif 290#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
index 18b1b3a223ab..9968362a2ee4 100644
--- a/arch/blackfin/mach-bf561/include/mach/bf561.h
+++ b/arch/blackfin/mach-bf561/include/mach/bf561.h
@@ -215,7 +215,7 @@
215#endif 215#endif
216 216
217#ifndef CPU 217#ifndef CPU
218#error Unknown CPU type - This kernel doesn't seem to be configured properly 218#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
219#endif 219#endif
220 220
221#endif /* __MACH_BF561_H__ */ 221#endif /* __MACH_BF561_H__ */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h b/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static int bfin_sir_hw_init(void)
114{
115 int ret = -ENODEV;
116#ifdef CONFIG_BFIN_SIR0
117 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
118 if (ret)
119 return ret;
120 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
121 if (ret)
122 return ret;
123#endif
124 return ret;
125}
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 0ea8666e6764..f79f6626b7ec 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -66,8 +66,12 @@
66 66
67#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) 67#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
68#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) 68#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
69#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
70#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) 71#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) 72#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
73#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
74#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
71 75
72#define BFIN_UART_NR_PORTS 1 76#define BFIN_UART_NR_PORTS 1
73 77
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index c14d63402e70..95d609f11c97 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -39,65 +39,15 @@
39/*include core specific register pointer definitions*/ 39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h> 40#include <asm/cdef_LPBlackfin.h>
41 41
42#include <asm/system.h>
43
44/*********************************************************************************** */ 42/*********************************************************************************** */
45/* System MMR Register Map */ 43/* System MMR Register Map */
46/*********************************************************************************** */ 44/*********************************************************************************** */
47 45
48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 46/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 47#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
50/* Writing to PLL_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_PLL_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1;
54
55 if (val == bfin_read_PLL_CTL())
56 return;
57
58 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1);
62 /* Only allow PPL Wakeup) */
63 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
64 bfin_write32(SICA_IWR1, 0);
65
66 bfin_write16(PLL_CTL, val);
67 SSYNC();
68 asm("IDLE;");
69
70 bfin_write32(SICA_IWR0, iwr0);
71 bfin_write32(SICA_IWR1, iwr1);
72 local_irq_restore(flags);
73}
74#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 48#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
75#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 49#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
76#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 50#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
77/* Writing to VR_CTL initiates a PLL relock sequence. */
78static __inline__ void bfin_write_VR_CTL(unsigned int val)
79{
80 unsigned long flags, iwr0, iwr1;
81
82 if (val == bfin_read_VR_CTL())
83 return;
84
85 local_irq_save(flags);
86 /* Enable the PLL Wakeup bit in SIC IWR */
87 iwr0 = bfin_read32(SICA_IWR0);
88 iwr1 = bfin_read32(SICA_IWR1);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
91 bfin_write32(SICA_IWR1, 0);
92
93 bfin_write16(VR_CTL, val);
94 SSYNC();
95 asm("IDLE;");
96
97 bfin_write32(SICA_IWR0, iwr0);
98 bfin_write32(SICA_IWR1, iwr1);
99 local_irq_restore(flags);
100}
101#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 51#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
102#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 52#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
103#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 53#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -1576,4 +1526,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1576#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() 1526#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1577#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) 1527#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1578 1528
1529/* These need to be last due to the cdef/linux inter-dependencies */
1530#include <asm/irq.h>
1531
1532/* Writing to PLL_CTL initiates a PLL relock sequence. */
1533static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1534{
1535 unsigned long flags, iwr0, iwr1;
1536
1537 if (val == bfin_read_PLL_CTL())
1538 return;
1539
1540 local_irq_save_hw(flags);
1541 /* Enable the PLL Wakeup bit in SIC IWR */
1542 iwr0 = bfin_read32(SICA_IWR0);
1543 iwr1 = bfin_read32(SICA_IWR1);
1544 /* Only allow PPL Wakeup) */
1545 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1546 bfin_write32(SICA_IWR1, 0);
1547
1548 bfin_write16(PLL_CTL, val);
1549 SSYNC();
1550 asm("IDLE;");
1551
1552 bfin_write32(SICA_IWR0, iwr0);
1553 bfin_write32(SICA_IWR1, iwr1);
1554 local_irq_restore_hw(flags);
1555}
1556
1557/* Writing to VR_CTL initiates a PLL relock sequence. */
1558static __inline__ void bfin_write_VR_CTL(unsigned int val)
1559{
1560 unsigned long flags, iwr0, iwr1;
1561
1562 if (val == bfin_read_VR_CTL())
1563 return;
1564
1565 local_irq_save_hw(flags);
1566 /* Enable the PLL Wakeup bit in SIC IWR */
1567 iwr0 = bfin_read32(SICA_IWR0);
1568 iwr1 = bfin_read32(SICA_IWR1);
1569 /* Only allow PPL Wakeup) */
1570 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1571 bfin_write32(SICA_IWR1, 0);
1572
1573 bfin_write16(VR_CTL, val);
1574 SSYNC();
1575 asm("IDLE;");
1576
1577 bfin_write32(SICA_IWR0, iwr0);
1578 bfin_write32(SICA_IWR1, iwr1);
1579 local_irq_restore_hw(flags);
1580}
1581
1579#endif /* _CDEF_BF561_H */ 1582#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 4eca2026bb92..d7c509759659 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -912,6 +912,9 @@
912#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 912#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
913#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 913#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
914 914
915/* SICA_SYSCR Masks */
916#define COREB_SRAM_INIT 0x0020
917
915/* SWRST Mask */ 918/* SWRST Mask */
916#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ 919#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
917#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ 920#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h
index 8bc46cd89a02..13647c71f1c7 100644
--- a/arch/blackfin/mach-bf561/include/mach/dma.h
+++ b/arch/blackfin/mach-bf561/include/mach/dma.h
@@ -1,13 +1,17 @@
1/***************************************************************************** 1/* mach/dma.h - arch-specific DMA defines
2* 2 *
3* BF-533/2/1 Specific Declarations 3 * Copyright 2004-2008 Analog Devices Inc.
4* 4 *
5****************************************************************************/ 5 * Licensed under the GPL-2 or later.
6 */
6 7
7#ifndef _MACH_DMA_H_ 8#ifndef _MACH_DMA_H_
8#define _MACH_DMA_H_ 9#define _MACH_DMA_H_
9 10
10#define MAX_BLACKFIN_DMA_CHANNEL 36 11#define MAX_DMA_CHANNELS 36
12
13/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
14#define MAX_DMA_SUSPEND_CHANNELS 32
11 15
12#define CH_PPI0 0 16#define CH_PPI0 0
13#define CH_PPI (CH_PPI0) 17#define CH_PPI (CH_PPI0)
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
new file mode 100644
index 000000000000..7882f79e1ade
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -0,0 +1,68 @@
1/*
2 * File: arch/blackfin/mach-bf561/include/mach/gpio.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9
10#ifndef _MACH_GPIO_H_
11#define _MACH_GPIO_H_
12
13#define MAX_BLACKFIN_GPIOS 48
14
15#define GPIO_PF0 0
16#define GPIO_PF1 1
17#define GPIO_PF2 2
18#define GPIO_PF3 3
19#define GPIO_PF4 4
20#define GPIO_PF5 5
21#define GPIO_PF6 6
22#define GPIO_PF7 7
23#define GPIO_PF8 8
24#define GPIO_PF9 9
25#define GPIO_PF10 10
26#define GPIO_PF11 11
27#define GPIO_PF12 12
28#define GPIO_PF13 13
29#define GPIO_PF14 14
30#define GPIO_PF15 15
31#define GPIO_PF16 16
32#define GPIO_PF17 17
33#define GPIO_PF18 18
34#define GPIO_PF19 19
35#define GPIO_PF20 20
36#define GPIO_PF21 21
37#define GPIO_PF22 22
38#define GPIO_PF23 23
39#define GPIO_PF24 24
40#define GPIO_PF25 25
41#define GPIO_PF26 26
42#define GPIO_PF27 27
43#define GPIO_PF28 28
44#define GPIO_PF29 29
45#define GPIO_PF30 30
46#define GPIO_PF31 31
47#define GPIO_PF32 32
48#define GPIO_PF33 33
49#define GPIO_PF34 34
50#define GPIO_PF35 35
51#define GPIO_PF36 36
52#define GPIO_PF37 37
53#define GPIO_PF38 38
54#define GPIO_PF39 39
55#define GPIO_PF40 40
56#define GPIO_PF41 41
57#define GPIO_PF42 42
58#define GPIO_PF43 43
59#define GPIO_PF44 44
60#define GPIO_PF45 45
61#define GPIO_PF46 46
62#define GPIO_PF47 47
63
64#define PORT_FIO0 GPIO_0
65#define PORT_FIO1 GPIO_16
66#define PORT_FIO2 GPIO_32
67
68#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_init.h b/arch/blackfin/mach-bf561/include/mach/mem_init.h
deleted file mode 100644
index e163260bca18..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/mem_init.h
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
32#if (CONFIG_SCLK_HZ > 119402985)
33#define SDRAM_tRP TRP_2
34#define SDRAM_tRP_num 2
35#define SDRAM_tRAS TRAS_7
36#define SDRAM_tRAS_num 7
37#define SDRAM_tRCD TRCD_2
38#define SDRAM_tWR TWR_2
39#endif
40#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
41#define SDRAM_tRP TRP_2
42#define SDRAM_tRP_num 2
43#define SDRAM_tRAS TRAS_6
44#define SDRAM_tRAS_num 6
45#define SDRAM_tRCD TRCD_2
46#define SDRAM_tWR TWR_2
47#endif
48#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
49#define SDRAM_tRP TRP_2
50#define SDRAM_tRP_num 2
51#define SDRAM_tRAS TRAS_5
52#define SDRAM_tRAS_num 5
53#define SDRAM_tRCD TRCD_2
54#define SDRAM_tWR TWR_2
55#endif
56#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
57#define SDRAM_tRP TRP_2
58#define SDRAM_tRP_num 2
59#define SDRAM_tRAS TRAS_4
60#define SDRAM_tRAS_num 4
61#define SDRAM_tRCD TRCD_2
62#define SDRAM_tWR TWR_2
63#endif
64#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
65#define SDRAM_tRP TRP_2
66#define SDRAM_tRP_num 2
67#define SDRAM_tRAS TRAS_3
68#define SDRAM_tRAS_num 3
69#define SDRAM_tRCD TRCD_2
70#define SDRAM_tWR TWR_2
71#endif
72#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
73#define SDRAM_tRP TRP_1
74#define SDRAM_tRP_num 1
75#define SDRAM_tRAS TRAS_4
76#define SDRAM_tRAS_num 3
77#define SDRAM_tRCD TRCD_1
78#define SDRAM_tWR TWR_2
79#endif
80#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
81#define SDRAM_tRP TRP_1
82#define SDRAM_tRP_num 1
83#define SDRAM_tRAS TRAS_3
84#define SDRAM_tRAS_num 3
85#define SDRAM_tRCD TRCD_1
86#define SDRAM_tWR TWR_2
87#endif
88#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
89#define SDRAM_tRP TRP_1
90#define SDRAM_tRP_num 1
91#define SDRAM_tRAS TRAS_2
92#define SDRAM_tRAS_num 2
93#define SDRAM_tRCD TRCD_1
94#define SDRAM_tWR TWR_2
95#endif
96#if (CONFIG_SCLK_HZ <= 29850746)
97#define SDRAM_tRP TRP_1
98#define SDRAM_tRP_num 1
99#define SDRAM_tRAS TRAS_1
100#define SDRAM_tRAS_num 1
101#define SDRAM_tRCD TRCD_1
102#define SDRAM_tWR TWR_2
103#endif
104#endif
105
106#if (CONFIG_MEM_MT48LC16M16A2TG_75)
107 /*SDRAM INFORMATION: */
108#define SDRAM_Tref 64 /* Refresh period in milliseconds */
109#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
110#define SDRAM_CL CL_3
111#endif
112
113#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114 /*SDRAM INFORMATION: */
115#define SDRAM_Tref 64 /* Refresh period in milliseconds */
116#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
117#define SDRAM_CL CL_3
118#endif
119
120#if (CONFIG_MEM_MT48LC8M32B2B5_7)
121 /*SDRAM INFORMATION: */
122#define SDRAM_Tref 64 /* Refresh period in milliseconds */
123#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124#define SDRAM_CL CL_3
125#endif
126
127#if (CONFIG_MEM_GENERIC_BOARD)
128 /*SDRAM INFORMATION: Modify this for your board */
129#define SDRAM_Tref 64 /* Refresh period in milliseconds */
130#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
131#define SDRAM_CL CL_3
132#endif
133
134/* Equation from section 17 (p17-46) of BF533 HRM */
135#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
136
137/* Enable SCLK Out */
138#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
139
140#if defined CONFIG_CLKIN_HALF
141#define CLKIN_HALF 1
142#else
143#define CLKIN_HALF 0
144#endif
145
146#if defined CONFIG_PLL_BYPASS
147#define PLL_BYPASS 1
148#else
149#define PLL_BYPASS 0
150#endif
151
152/***************************************Currently Not Being Used *********************************/
153#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
154#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
155#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
156#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
158
159#if (flash_EBIU_AMBCTL_TT > 3)
160#define flash_EBIU_AMBCTL0_TT B0TT_4
161#endif
162#if (flash_EBIU_AMBCTL_TT == 3)
163#define flash_EBIU_AMBCTL0_TT B0TT_3
164#endif
165#if (flash_EBIU_AMBCTL_TT == 2)
166#define flash_EBIU_AMBCTL0_TT B0TT_2
167#endif
168#if (flash_EBIU_AMBCTL_TT < 2)
169#define flash_EBIU_AMBCTL0_TT B0TT_1
170#endif
171
172#if (flash_EBIU_AMBCTL_ST > 3)
173#define flash_EBIU_AMBCTL0_ST B0ST_4
174#endif
175#if (flash_EBIU_AMBCTL_ST == 3)
176#define flash_EBIU_AMBCTL0_ST B0ST_3
177#endif
178#if (flash_EBIU_AMBCTL_ST == 2)
179#define flash_EBIU_AMBCTL0_ST B0ST_2
180#endif
181#if (flash_EBIU_AMBCTL_ST < 2)
182#define flash_EBIU_AMBCTL0_ST B0ST_1
183#endif
184
185#if (flash_EBIU_AMBCTL_HT > 2)
186#define flash_EBIU_AMBCTL0_HT B0HT_3
187#endif
188#if (flash_EBIU_AMBCTL_HT == 2)
189#define flash_EBIU_AMBCTL0_HT B0HT_2
190#endif
191#if (flash_EBIU_AMBCTL_HT == 1)
192#define flash_EBIU_AMBCTL0_HT B0HT_1
193#endif
194#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
195#define flash_EBIU_AMBCTL0_HT B0HT_0
196#endif
197#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
198#define flash_EBIU_AMBCTL0_HT B0HT_1
199#endif
200
201#if (flash_EBIU_AMBCTL_WAT > 14)
202#define flash_EBIU_AMBCTL0_WAT B0WAT_15
203#endif
204#if (flash_EBIU_AMBCTL_WAT == 14)
205#define flash_EBIU_AMBCTL0_WAT B0WAT_14
206#endif
207#if (flash_EBIU_AMBCTL_WAT == 13)
208#define flash_EBIU_AMBCTL0_WAT B0WAT_13
209#endif
210#if (flash_EBIU_AMBCTL_WAT == 12)
211#define flash_EBIU_AMBCTL0_WAT B0WAT_12
212#endif
213#if (flash_EBIU_AMBCTL_WAT == 11)
214#define flash_EBIU_AMBCTL0_WAT B0WAT_11
215#endif
216#if (flash_EBIU_AMBCTL_WAT == 10)
217#define flash_EBIU_AMBCTL0_WAT B0WAT_10
218#endif
219#if (flash_EBIU_AMBCTL_WAT == 9)
220#define flash_EBIU_AMBCTL0_WAT B0WAT_9
221#endif
222#if (flash_EBIU_AMBCTL_WAT == 8)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_8
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 7)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_7
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 6)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_6
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 5)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_5
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 4)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_4
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 3)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_3
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 2)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_2
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 1)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_1
245#endif
246
247#if (flash_EBIU_AMBCTL_RAT > 14)
248#define flash_EBIU_AMBCTL0_RAT B0RAT_15
249#endif
250#if (flash_EBIU_AMBCTL_RAT == 14)
251#define flash_EBIU_AMBCTL0_RAT B0RAT_14
252#endif
253#if (flash_EBIU_AMBCTL_RAT == 13)
254#define flash_EBIU_AMBCTL0_RAT B0RAT_13
255#endif
256#if (flash_EBIU_AMBCTL_RAT == 12)
257#define flash_EBIU_AMBCTL0_RAT B0RAT_12
258#endif
259#if (flash_EBIU_AMBCTL_RAT == 11)
260#define flash_EBIU_AMBCTL0_RAT B0RAT_11
261#endif
262#if (flash_EBIU_AMBCTL_RAT == 10)
263#define flash_EBIU_AMBCTL0_RAT B0RAT_10
264#endif
265#if (flash_EBIU_AMBCTL_RAT == 9)
266#define flash_EBIU_AMBCTL0_RAT B0RAT_9
267#endif
268#if (flash_EBIU_AMBCTL_RAT == 8)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_8
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 7)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_7
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 6)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_6
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 5)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_5
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 4)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_4
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 3)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_3
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 2)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_2
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 1)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_1
291#endif
292
293#define flash_EBIU_AMBCTL0 \
294 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
295 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index f1d4c0637bd2..419dffdc96eb 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -85,4 +85,84 @@
85#define L1_SCRATCH_START COREA_L1_SCRATCH_START 85#define L1_SCRATCH_START COREA_L1_SCRATCH_START
86#define L1_SCRATCH_LENGTH 0x1000 86#define L1_SCRATCH_LENGTH 0x1000
87 87
88#ifdef __ASSEMBLY__
89
90/*
91 * The following macros both return the address of the PDA for the
92 * current core.
93 *
94 * In its first safe (and hairy) form, the macro neither clobbers any
95 * register aside of the output Preg, nor uses the stack, since it
96 * could be called with an invalid stack pointer, or the current stack
97 * space being uncovered by any CPLB (e.g. early exception handling).
98 *
99 * The constraints on the second form are a bit relaxed, and the code
100 * is allowed to use the specified Dreg for determining the PDA
101 * address to be returned into Preg.
102 */
103#ifdef CONFIG_SMP
104#define GET_PDA_SAFE(preg) \
105 preg.l = lo(DSPID); \
106 preg.h = hi(DSPID); \
107 preg = [preg]; \
108 preg = preg << 2; \
109 preg = preg << 2; \
110 preg = preg << 2; \
111 preg = preg << 2; \
112 preg = preg << 2; \
113 preg = preg << 2; \
114 preg = preg << 2; \
115 preg = preg << 2; \
116 preg = preg << 2; \
117 preg = preg << 2; \
118 preg = preg << 2; \
119 preg = preg << 2; \
120 if cc jump 2f; \
121 cc = preg == 0x0; \
122 preg.l = _cpu_pda; \
123 preg.h = _cpu_pda; \
124 if !cc jump 3f; \
1251: \
126 /* preg = 0x0; */ \
127 cc = !cc; /* restore cc to 0 */ \
128 jump 4f; \
1292: \
130 cc = preg == 0x0; \
131 preg.l = _cpu_pda; \
132 preg.h = _cpu_pda; \
133 if cc jump 4f; \
134 /* preg = 0x1000000; */ \
135 cc = !cc; /* restore cc to 1 */ \
1363: \
137 preg = [preg]; \
1384:
139
140#define GET_PDA(preg, dreg) \
141 preg.l = lo(DSPID); \
142 preg.h = hi(DSPID); \
143 dreg = [preg]; \
144 preg.l = _cpu_pda; \
145 preg.h = _cpu_pda; \
146 cc = bittst(dreg, 0); \
147 if !cc jump 1f; \
148 preg = [preg]; \
1491: \
150
151#define GET_CPUID(preg, dreg) \
152 preg.l = lo(DSPID); \
153 preg.h = hi(DSPID); \
154 dreg = [preg]; \
155 dreg = ROT dreg BY -1; \
156 dreg = CC;
157
158#else
159#define GET_PDA_SAFE(preg) \
160 preg.l = _cpu_pda; \
161 preg.h = _cpu_pda;
162
163#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
164#endif /* CONFIG_SMP */
165
166#endif /* __ASSEMBLY__ */
167
88#endif /* _MEM_MAP_533_H_ */ 168#endif /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
new file mode 100644
index 000000000000..f9e65ebe81b2
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/smp.h
@@ -0,0 +1,22 @@
1#ifndef _MACH_BF561_SMP
2#define _MACH_BF561_SMP
3
4struct task_struct;
5
6void platform_init_cpus(void);
7
8void platform_prepare_cpus(unsigned int max_cpus);
9
10int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
11
12void platform_secondary_init(unsigned int cpu);
13
14void platform_request_ipi(int (*handler)(int, void *));
15
16void platform_send_ipi(cpumask_t callmap);
17
18void platform_send_ipi_cpu(unsigned int cpu);
19
20void platform_clear_ipi(unsigned int cpu);
21
22#endif /* !_MACH_BF561_SMP */
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
new file mode 100644
index 000000000000..35280f06b7b6
--- /dev/null
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -0,0 +1,215 @@
1/*
2 * File: arch/blackfin/mach-bf561/secondary.S
3 * Based on: arch/blackfin/mach-bf561/head.S
4 * Author: Philippe Gerum <rpm@xenomai.org>
5 *
6 * Copyright 2007 Analog Devices Inc.
7 *
8 * Description: BF561 coreB bootstrap file
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, see the file COPYING, or write
22 * to the Free Software Foundation, Inc.,
23 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 */
25
26#include <linux/linkage.h>
27#include <linux/init.h>
28#include <asm/blackfin.h>
29#include <asm/asm-offsets.h>
30
31__INIT
32
33/* Lay the initial stack into the L1 scratch area of Core B */
34#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
35
36ENTRY(_coreb_trampoline_start)
37 /* Set the SYSCFG register */
38 R0 = 0x36;
39 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
40 R0 = 0;
41
42 /*Clear Out All the data and pointer Registers*/
43 R1 = R0;
44 R2 = R0;
45 R3 = R0;
46 R4 = R0;
47 R5 = R0;
48 R6 = R0;
49 R7 = R0;
50
51 P0 = R0;
52 P1 = R0;
53 P2 = R0;
54 P3 = R0;
55 P4 = R0;
56 P5 = R0;
57
58 LC0 = r0;
59 LC1 = r0;
60 L0 = r0;
61 L1 = r0;
62 L2 = r0;
63 L3 = r0;
64
65 /* Clear Out All the DAG Registers*/
66 B0 = r0;
67 B1 = r0;
68 B2 = r0;
69 B3 = r0;
70
71 I0 = r0;
72 I1 = r0;
73 I2 = r0;
74 I3 = r0;
75
76 M0 = r0;
77 M1 = r0;
78 M2 = r0;
79 M3 = r0;
80
81 /* Turn off the icache */
82 p0.l = LO(IMEM_CONTROL);
83 p0.h = HI(IMEM_CONTROL);
84 R1 = [p0];
85 R0 = ~ENICPLB;
86 R0 = R0 & R1;
87
88 /* Anomaly 05000125 */
89#ifdef ANOMALY_05000125
90 CLI R2;
91 SSYNC;
92#endif
93 [p0] = R0;
94 SSYNC;
95#ifdef ANOMALY_05000125
96 STI R2;
97#endif
98
99 /* Turn off the dcache */
100 p0.l = LO(DMEM_CONTROL);
101 p0.h = HI(DMEM_CONTROL);
102 R1 = [p0];
103 R0 = ~ENDCPLB;
104 R0 = R0 & R1;
105
106 /* Anomaly 05000125 */
107#ifdef ANOMALY_05000125
108 CLI R2;
109 SSYNC;
110#endif
111 [p0] = R0;
112 SSYNC;
113#ifdef ANOMALY_05000125
114 STI R2;
115#endif
116
117 /* in case of double faults, save a few things */
118 p0.l = _init_retx_coreb;
119 p0.h = _init_retx_coreb;
120 R0 = RETX;
121 [P0] = R0;
122
123#ifdef CONFIG_DEBUG_DOUBLEFAULT
124 /* Only save these if we are storing them,
125 * This happens here, since L1 gets clobbered
126 * below
127 */
128 GET_PDA(p0, r0);
129 r7 = [p0 + PDA_RETX];
130 p1.l = _init_saved_retx_coreb;
131 p1.h = _init_saved_retx_coreb;
132 [p1] = r7;
133
134 r7 = [p0 + PDA_DCPLB];
135 p1.l = _init_saved_dcplb_fault_addr_coreb;
136 p1.h = _init_saved_dcplb_fault_addr_coreb;
137 [p1] = r7;
138
139 r7 = [p0 + PDA_ICPLB];
140 p1.l = _init_saved_icplb_fault_addr_coreb;
141 p1.h = _init_saved_icplb_fault_addr_coreb;
142 [p1] = r7;
143
144 r7 = [p0 + PDA_SEQSTAT];
145 p1.l = _init_saved_seqstat_coreb;
146 p1.h = _init_saved_seqstat_coreb;
147 [p1] = r7;
148#endif
149
150 /* Initialize stack pointer */
151 sp.l = lo(INITIAL_STACK);
152 sp.h = hi(INITIAL_STACK);
153 fp = sp;
154 usp = sp;
155
156 /* This section keeps the processor in supervisor mode
157 * during core B startup. Branches to the idle task.
158 */
159
160 /* EVT15 = _real_start */
161
162 p0.l = lo(EVT15);
163 p0.h = hi(EVT15);
164 p1.l = _coreb_start;
165 p1.h = _coreb_start;
166 [p0] = p1;
167 csync;
168
169 p0.l = lo(IMASK);
170 p0.h = hi(IMASK);
171 p1.l = IMASK_IVG15;
172 p1.h = 0x0;
173 [p0] = p1;
174 csync;
175
176 raise 15;
177 p0.l = .LWAIT_HERE;
178 p0.h = .LWAIT_HERE;
179 reti = p0;
180#if defined(ANOMALY_05000281)
181 nop; nop; nop;
182#endif
183 rti;
184
185.LWAIT_HERE:
186 jump .LWAIT_HERE;
187ENDPROC(_coreb_trampoline_start)
188ENTRY(_coreb_trampoline_end)
189
190ENTRY(_coreb_start)
191 [--sp] = reti;
192
193 p0.l = lo(WDOGB_CTL);
194 p0.h = hi(WDOGB_CTL);
195 r0 = 0xAD6(z);
196 w[p0] = r0; /* Clear the watchdog. */
197 ssync;
198
199 /*
200 * switch to IDLE stack.
201 */
202 p0.l = _secondary_stack;
203 p0.h = _secondary_stack;
204 sp = [p0];
205 usp = sp;
206 fp = sp;
207 sp += -12;
208 call _init_pda
209 sp += 12;
210 call _secondary_start_kernel;
211.L_exit:
212 jump.s .L_exit;
213ENDPROC(_coreb_start)
214
215__FINIT
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
new file mode 100644
index 000000000000..9b27e698c0b2
--- /dev/null
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -0,0 +1,167 @@
1/*
2 * File: arch/blackfin/mach-bf561/smp.c
3 * Author: Philippe Gerum <rpm@xenomai.org>
4 *
5 * Copyright 2007 Analog Devices Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see the file COPYING, or write
19 * to the Free Software Foundation, Inc.,
20 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/sched.h>
26#include <linux/delay.h>
27#include <asm/smp.h>
28#include <asm/dma.h>
29
30static DEFINE_SPINLOCK(boot_lock);
31
32static cpumask_t cpu_callin_map;
33
34/*
35 * platform_init_cpus() - Tell the world about how many cores we
36 * have. This is called while setting up the architecture support
37 * (setup_arch()), so don't be too demanding here with respect to
38 * available kernel services.
39 */
40
41void __init platform_init_cpus(void)
42{
43 cpu_set(0, cpu_possible_map); /* CoreA */
44 cpu_set(1, cpu_possible_map); /* CoreB */
45}
46
47void __init platform_prepare_cpus(unsigned int max_cpus)
48{
49 int len;
50
51 len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
52 BUG_ON(len > L1_CODE_LENGTH);
53
54 dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
55
56 /* Both cores ought to be present on a bf561! */
57 cpu_set(0, cpu_present_map); /* CoreA */
58 cpu_set(1, cpu_present_map); /* CoreB */
59
60 printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
61}
62
63int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
64{
65 return -EINVAL;
66}
67
68void __cpuinit platform_secondary_init(unsigned int cpu)
69{
70 local_irq_disable();
71
72 /* Clone setup for peripheral interrupt sources from CoreA. */
73 bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
74 bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
75 SSYNC();
76
77 /* Clone setup for IARs from CoreA. */
78 bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
79 bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
80 bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
81 bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
82 bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
83 bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
84 bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
85 bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
86 SSYNC();
87
88 local_irq_enable();
89
90 /* Calibrate loops per jiffy value. */
91 calibrate_delay();
92
93 /* Store CPU-private information to the cpu_data array. */
94 bfin_setup_cpudata(cpu);
95
96 /* We are done with local CPU inits, unblock the boot CPU. */
97 cpu_set(cpu, cpu_callin_map);
98 spin_lock(&boot_lock);
99 spin_unlock(&boot_lock);
100}
101
102int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
103{
104 unsigned long timeout;
105
106 /* CoreB already running?! */
107 BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0);
108
109 printk(KERN_INFO "Booting Core B.\n");
110
111 spin_lock(&boot_lock);
112
113 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
114 SSYNC();
115 bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
116 SSYNC();
117
118 timeout = jiffies + 1 * HZ;
119 while (time_before(jiffies, timeout)) {
120 if (cpu_isset(cpu, cpu_callin_map))
121 break;
122 udelay(100);
123 barrier();
124 }
125
126 spin_unlock(&boot_lock);
127
128 return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS;
129}
130
131void __init platform_request_ipi(irq_handler_t handler)
132{
133 int ret;
134
135 ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
136 "SMP interrupt", handler);
137 if (ret)
138 panic("Cannot request supplemental interrupt 0 for IPI service\n");
139}
140
141void platform_send_ipi(cpumask_t callmap)
142{
143 unsigned int cpu;
144
145 for_each_cpu_mask(cpu, callmap) {
146 BUG_ON(cpu >= 2);
147 SSYNC();
148 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
149 SSYNC();
150 }
151}
152
153void platform_send_ipi_cpu(unsigned int cpu)
154{
155 BUG_ON(cpu >= 2);
156 SSYNC();
157 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
158 SSYNC();
159}
160
161void platform_clear_ipi(unsigned int cpu)
162{
163 BUG_ON(cpu >= 2);
164 SSYNC();
165 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
166 SSYNC();
167}
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