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-rw-r--r--arch/blackfin/mach-bf561/secondary.S20
1 files changed, 4 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 097550f7b558..f72a6af20c4f 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -85,16 +85,10 @@ ENTRY(_coreb_trampoline_start)
85 R0 = ~ENICPLB; 85 R0 = ~ENICPLB;
86 R0 = R0 & R1; 86 R0 = R0 & R1;
87 87
88 /* Anomaly 05000125 */ 88 /* Disabling of CPLBs should be proceeded by a CSYNC */
89#ifdef ANOMALY_05000125 89 CSYNC;
90 CLI R2;
91 SSYNC;
92#endif
93 [p0] = R0; 90 [p0] = R0;
94 SSYNC; 91 SSYNC;
95#ifdef ANOMALY_05000125
96 STI R2;
97#endif
98 92
99 /* Turn off the dcache */ 93 /* Turn off the dcache */
100 p0.l = LO(DMEM_CONTROL); 94 p0.l = LO(DMEM_CONTROL);
@@ -103,16 +97,10 @@ ENTRY(_coreb_trampoline_start)
103 R0 = ~ENDCPLB; 97 R0 = ~ENDCPLB;
104 R0 = R0 & R1; 98 R0 = R0 & R1;
105 99
106 /* Anomaly 05000125 */ 100 /* Disabling of CPLBs should be proceeded by a CSYNC */
107#ifdef ANOMALY_05000125 101 CSYNC;
108 CLI R2;
109 SSYNC;
110#endif
111 [p0] = R0; 102 [p0] = R0;
112 SSYNC; 103 SSYNC;
113#ifdef ANOMALY_05000125
114 STI R2;
115#endif
116 104
117 /* in case of double faults, save a few things */ 105 /* in case of double faults, save a few things */
118 p0.l = _init_retx_coreb; 106 p0.l = _init_retx_coreb;