diff options
Diffstat (limited to 'arch/blackfin/mach-bf561/include')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/defBF561.h | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index c2f9c8f54eab..4c8e36b7fb33 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h | |||
| @@ -1096,53 +1096,6 @@ | |||
| 1096 | 1096 | ||
| 1097 | /* ********** DMA CONTROLLER MASKS *********************8 */ | 1097 | /* ********** DMA CONTROLLER MASKS *********************8 */ |
| 1098 | 1098 | ||
| 1099 | /* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ | ||
| 1100 | #define DMAEN 0x00000001 /* Channel Enable */ | ||
| 1101 | #define WNR 0x00000002 /* Channel Direction (W/R*) */ | ||
| 1102 | #define WDSIZE_8 0x00000000 /* Word Size 8 bits */ | ||
| 1103 | #define WDSIZE_16 0x00000004 /* Word Size 16 bits */ | ||
| 1104 | #define WDSIZE_32 0x00000008 /* Word Size 32 bits */ | ||
| 1105 | #define DMA2D 0x00000010 /* 2D/1D* Mode */ | ||
| 1106 | #define RESTART 0x00000020 /* Restart */ | ||
| 1107 | #define DI_SEL 0x00000040 /* Data Interrupt Select */ | ||
| 1108 | #define DI_EN 0x00000080 /* Data Interrupt Enable */ | ||
| 1109 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | ||
| 1110 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | ||
| 1111 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | ||
| 1112 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | ||
| 1113 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | ||
| 1114 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | ||
| 1115 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | ||
| 1116 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | ||
| 1117 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | ||
| 1118 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | ||
| 1119 | #define NDSIZE 0x00000900 /* Next Descriptor Size */ | ||
| 1120 | #define DMAFLOW 0x00007000 /* Flow Control */ | ||
| 1121 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
| 1122 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
| 1123 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | ||
| 1124 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | ||
| 1125 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | ||
| 1126 | |||
| 1127 | #define DMAEN_P 0 /* Channel Enable */ | ||
| 1128 | #define WNR_P 1 /* Channel Direction (W/R*) */ | ||
| 1129 | #define DMA2D_P 4 /* 2D/1D* Mode */ | ||
| 1130 | #define RESTART_P 5 /* Restart */ | ||
| 1131 | #define DI_SEL_P 6 /* Data Interrupt Select */ | ||
| 1132 | #define DI_EN_P 7 /* Data Interrupt Enable */ | ||
| 1133 | |||
| 1134 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ | ||
| 1135 | |||
| 1136 | #define DMA_DONE 0x00000001 /* DMA Done Indicator */ | ||
| 1137 | #define DMA_ERR 0x00000002 /* DMA Error Indicator */ | ||
| 1138 | #define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ | ||
| 1139 | #define DMA_RUN 0x00000008 /* DMA Running Indicator */ | ||
| 1140 | |||
| 1141 | #define DMA_DONE_P 0 /* DMA Done Indicator */ | ||
| 1142 | #define DMA_ERR_P 1 /* DMA Error Indicator */ | ||
| 1143 | #define DFETCH_P 2 /* Descriptor Fetch Indicator */ | ||
| 1144 | #define DMA_RUN_P 3 /* DMA Running Indicator */ | ||
| 1145 | |||
| 1146 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ | 1099 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ |
| 1147 | 1100 | ||
| 1148 | #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ | 1101 | #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ |