diff options
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/defBF561.h')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/defBF561.h | 94 |
1 files changed, 17 insertions, 77 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 2674f0097576..79e048d452e0 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h | |||
| @@ -28,32 +28,29 @@ | |||
| 28 | #define CHIPID 0xFFC00014 /* Chip ID Register */ | 28 | #define CHIPID 0xFFC00014 /* Chip ID Register */ |
| 29 | 29 | ||
| 30 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | 30 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ |
| 31 | #define SWRST SICA_SWRST | ||
| 32 | #define SYSCR SICA_SYSCR | ||
| 33 | #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) | 31 | #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) |
| 34 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) | 32 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) |
| 35 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) | 33 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) |
| 36 | #define RESET_SOFTWARE (SWRST_OCCURRED) | 34 | #define RESET_SOFTWARE (SWRST_OCCURRED) |
| 37 | 35 | ||
| 38 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | 36 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
| 39 | #define SICA_SWRST 0xFFC00100 /* Software Reset register */ | 37 | #define SWRST 0xFFC00100 /* Software Reset register */ |
| 40 | #define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ | 38 | #define SYSCR 0xFFC00104 /* System Reset Configuration register */ |
| 41 | #define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ | 39 | #define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ |
| 42 | #define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ | 40 | #define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ |
| 43 | #define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ | 41 | #define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ |
| 44 | #define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ | 42 | #define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ |
| 45 | #define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ | 43 | #define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ |
| 46 | #define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ | 44 | #define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ |
| 47 | #define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ | 45 | #define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ |
| 48 | #define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ | 46 | #define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ |
| 49 | #define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ | 47 | #define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ |
| 50 | #define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ | 48 | #define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ |
| 51 | #define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ | 49 | #define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ |
| 52 | #define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ | 50 | #define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ |
| 53 | #define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ | 51 | #define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ |
| 54 | #define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ | 52 | #define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ |
| 55 | #define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ | 53 | #define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ |
| 56 | #define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ | ||
| 57 | 54 | ||
| 58 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ | 55 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ |
| 59 | #define SICB_SWRST 0xFFC01100 /* reserved */ | 56 | #define SICB_SWRST 0xFFC01100 /* reserved */ |
| @@ -1271,63 +1268,6 @@ | |||
| 1271 | #define PF14_P 14 | 1268 | #define PF14_P 14 |
| 1272 | #define PF15_P 15 | 1269 | #define PF15_P 15 |
| 1273 | 1270 | ||
| 1274 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ | ||
| 1275 | |||
| 1276 | /* SPI_CTL Masks */ | ||
| 1277 | #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ | ||
| 1278 | #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ | ||
| 1279 | #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ | ||
| 1280 | #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ | ||
| 1281 | #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ | ||
| 1282 | #define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ | ||
| 1283 | #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ | ||
| 1284 | #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ | ||
| 1285 | #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ | ||
| 1286 | #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ | ||
| 1287 | #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ | ||
| 1288 | #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ | ||
| 1289 | |||
| 1290 | /* SPI_FLG Masks */ | ||
| 1291 | #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 1292 | #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 1293 | #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 1294 | #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 1295 | #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 1296 | #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 1297 | #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 1298 | #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 1299 | #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 1300 | #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 1301 | #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 1302 | #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 1303 | #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 1304 | #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 1305 | |||
| 1306 | /* SPI_FLG Bit Positions */ | ||
| 1307 | #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 1308 | #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 1309 | #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 1310 | #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 1311 | #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 1312 | #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 1313 | #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 1314 | #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 1315 | #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 1316 | #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 1317 | #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 1318 | #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 1319 | #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 1320 | #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 1321 | |||
| 1322 | /* SPI_STAT Masks */ | ||
| 1323 | #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ | ||
| 1324 | #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ | ||
| 1325 | #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ | ||
| 1326 | #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
| 1327 | #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ | ||
| 1328 | #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
| 1329 | #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ | ||
| 1330 | |||
| 1331 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ | 1271 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ |
| 1332 | 1272 | ||
| 1333 | /* AMGCTL Masks */ | 1273 | /* AMGCTL Masks */ |