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Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/anomaly.h')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h89
1 files changed, 46 insertions, 43 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index dccd396cd931..94b8e277f09d 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -18,19 +18,19 @@
18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
19#endif 19#endif
20 20
21/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
22#define ANOMALY_05000074 (1) 22#define ANOMALY_05000074 (1)
23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) 24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
25/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ 25/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
26#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) 26#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
27/* Testset instructions restricted to 32-bit aligned memory locations */ 27/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
28#define ANOMALY_05000120 (1) 28#define ANOMALY_05000120 (1)
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1) 30#define ANOMALY_05000122 (1)
31/* Erroneous exception when enabling cache */ 31/* Erroneous Exception when Enabling Cache */
32#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) 32#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
33/* Signbits instruction not functional under certain conditions */ 33/* SIGNBITS Instruction Not Functional under Certain Conditions */
34#define ANOMALY_05000127 (1) 34#define ANOMALY_05000127 (1)
35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ 35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) 36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
@@ -40,7 +40,7 @@
40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) 40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
41/* Allowing the SPORT RX FIFO to fill will cause an overflow */ 41/* Allowing the SPORT RX FIFO to fill will cause an overflow */
42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) 42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
43/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ 43/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
44#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) 44#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ 45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) 46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
@@ -52,7 +52,7 @@
52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) 52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ 53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) 54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
55/* IMDMA S1/D1 channel may stall */ 55/* IMDMA S1/D1 Channel May Stall */
56#define ANOMALY_05000149 (1) 56#define ANOMALY_05000149 (1)
57/* DMA engine may lose data due to incorrect handshaking */ 57/* DMA engine may lose data due to incorrect handshaking */
58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) 58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
@@ -66,7 +66,7 @@
66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) 66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ 67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) 68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
69/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ 69/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
70#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) 70#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ 71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) 72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
@@ -76,17 +76,17 @@
76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) 76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
77/* DMEM_CONTROL<12> is not set on Reset */ 77/* DMEM_CONTROL<12> is not set on Reset */
78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) 78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
79/* SPORT transmit data is not gated by external frame sync in certain conditions */ 79/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
80#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) 80#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
81/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ 81/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
82#define ANOMALY_05000166 (1) 82#define ANOMALY_05000166 (1)
83/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ 83/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
84#define ANOMALY_05000167 (1) 84#define ANOMALY_05000167 (1)
85/* SDRAM auto-refresh and subsequent Power Ups */ 85/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
86#define ANOMALY_05000168 (__SILICON_REVISION__ < 5) 86#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
87/* DATA CPLB page miss can result in lost write-through cache data writes */ 87/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
88#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) 88#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
89/* Boot-ROM code modifies SICA_IWRx wakeup registers */ 89/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
90#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) 90#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
91/* DSPID register values incorrect */ 91/* DSPID register values incorrect */
92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) 92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
@@ -96,29 +96,29 @@
96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) 96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
97/* Overlapping Sequencer and Memory Stalls */ 97/* Overlapping Sequencer and Memory Stalls */
98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5) 98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
99/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ 99/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5) 100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ 101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) 102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
104#define ANOMALY_05000180 (1) 104#define ANOMALY_05000180 (1)
105/* Disabling the PPI resets the PPI configuration registers */ 105/* Disabling the PPI Resets the PPI Configuration Registers */
106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5) 106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
107/* IMDMA does not operate to full speed for 600MHz and higher devices */ 107/* Internal Memory DMA Does Not Operate at Full Speed */
108#define ANOMALY_05000182 (1) 108#define ANOMALY_05000182 (1)
109/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ 109/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5) 110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
111/* PPI TX Mode with 2 External Frame Syncs */ 111/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5) 112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
113/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ 113/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5) 114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
115/* IMDMA Corrupted Data after a Halt */ 115/* IMDMA Corrupted Data after a Halt */
116#define ANOMALY_05000187 (1) 116#define ANOMALY_05000187 (1)
117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ 117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5) 118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
119/* False Protection Exceptions */ 119/* False Protection Exceptions when Speculative Fetch Is Cancelled */
120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) 120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
121/* PPI not functional at core voltage < 1Volt */ 121/* PPI Not Functional at Core Voltage < 1Volt */
122#define ANOMALY_05000190 (1) 122#define ANOMALY_05000190 (1)
123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ 123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) 124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
@@ -126,7 +126,7 @@
126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) 126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
127/* Restarting SPORT in Specific Modes May Cause Data Corruption */ 127/* Restarting SPORT in Specific Modes May Cause Data Corruption */
128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5) 128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
129/* Failing MMR Accesses When Stalled by Preceding Memory Read */ 129/* Failing MMR Accesses when Preceding Memory Read Stalls */
130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) 130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
131/* Current DMA Address Shows Wrong Value During Carry Fix */ 131/* Current DMA Address Shows Wrong Value During Carry Fix */
132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5) 132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
@@ -134,9 +134,9 @@
134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) 134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
135/* Possible Infinite Stall with Specific Dual-DAG Situation */ 135/* Possible Infinite Stall with Specific Dual-DAG Situation */
136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) 136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
137/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ 137/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5) 138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
139/* Specific sequence that can cause DMA error or DMA stopping */ 139/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5) 140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
141/* Recovery from "Brown-Out" Condition */ 141/* Recovery from "Brown-Out" Condition */
142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5) 142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
@@ -158,7 +158,7 @@
158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) 158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
159/* UART STB Bit Incorrectly Affects Receiver Setting */ 159/* UART STB Bit Incorrectly Affects Receiver Setting */
160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) 160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
161/* SPORT data transmit lines are incorrectly driven in multichannel mode */ 161/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ 163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
@@ -166,7 +166,7 @@
166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
167/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 167/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5) 168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
169/* TESTSET operation forces stall on the other core */ 169/* TESTSET Operation Forces Stall on the Other Core */
170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5) 170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) 172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
@@ -192,9 +192,9 @@
192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) 192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) 194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
195/* IMDMA destination IRQ status must be read prior to using IMDMA */ 195/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3) 196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
197/* IMDMA may corrupt data under certain conditions */ 197/* IMDMA May Corrupt Data under Certain Conditions */
198#define ANOMALY_05000267 (1) 198#define ANOMALY_05000267 (1)
199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ 199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
200#define ANOMALY_05000269 (1) 200#define ANOMALY_05000269 (1)
@@ -202,7 +202,7 @@
202#define ANOMALY_05000270 (1) 202#define ANOMALY_05000270 (1)
203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
204#define ANOMALY_05000272 (1) 204#define ANOMALY_05000272 (1)
205/* Data cache write back to external synchronous memory may be lost */ 205/* Data Cache Write Back to External Synchronous Memory May Be Lost */
206#define ANOMALY_05000274 (1) 206#define ANOMALY_05000274 (1)
207/* PPI Timing and Sampling Information Updates */ 207/* PPI Timing and Sampling Information Updates */
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) 208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
@@ -212,17 +212,17 @@
212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) 212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) 214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
215/* False Hardware Error Exception When ISR Context Is Not Restored */ 215/* False Hardware Error Exception when ISR Context Is Not Restored */
216#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) 216#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
217/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ 217/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
218#define ANOMALY_05000283 (1) 218#define ANOMALY_05000283 (1)
219/* A read will receive incorrect data under certain conditions */ 219/* Reads Will Receive Incorrect Data under Certain Conditions */
220#define ANOMALY_05000287 (__SILICON_REVISION__ < 5) 220#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
221/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 221/* SPORTs May Receive Bad Data If FIFOs Fill Up */
222#define ANOMALY_05000288 (__SILICON_REVISION__ < 5) 222#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
223/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 223/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
224#define ANOMALY_05000301 (1) 224#define ANOMALY_05000301 (1)
225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 225/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
226#define ANOMALY_05000302 (1) 226#define ANOMALY_05000302 (1)
227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ 227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
@@ -230,25 +230,25 @@
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) 230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
231/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 231/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
232#define ANOMALY_05000310 (1) 232#define ANOMALY_05000310 (1)
233/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 233/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
234#define ANOMALY_05000312 (1) 234#define ANOMALY_05000312 (1)
235/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 235/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
236#define ANOMALY_05000313 (1) 236#define ANOMALY_05000313 (1)
237/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ 237/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
238#define ANOMALY_05000315 (1) 238#define ANOMALY_05000315 (1)
239/* PF2 Output Remains Asserted After SPI Master Boot */ 239/* PF2 Output Remains Asserted after SPI Master Boot */
240#define ANOMALY_05000320 (__SILICON_REVISION__ > 3) 240#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
241/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ 241/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
242#define ANOMALY_05000323 (1) 242#define ANOMALY_05000323 (1)
243/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ 243/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
244#define ANOMALY_05000326 (__SILICON_REVISION__ > 3) 244#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
245/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ 245/* 24-Bit SPI Boot Mode Is Not Functional */
246#define ANOMALY_05000331 (__SILICON_REVISION__ < 5) 246#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
247/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ 247/* Slave SPI Boot Mode Is Not Functional */
248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) 248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
249/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ 249/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) 250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
251/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ 251/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5) 252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ 253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5) 254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
@@ -276,7 +276,7 @@
276#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) 276#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
277/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 277/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
278#define ANOMALY_05000443 (1) 278#define ANOMALY_05000443 (1)
279/* False Hardware Error when RETI points to invalid memory */ 279/* False Hardware Error when RETI Points to Invalid Memory */
280#define ANOMALY_05000461 (1) 280#define ANOMALY_05000461 (1)
281 281
282/* Anomalies that don't exist on this proc */ 282/* Anomalies that don't exist on this proc */
@@ -284,6 +284,7 @@
284#define ANOMALY_05000158 (0) 284#define ANOMALY_05000158 (0)
285#define ANOMALY_05000183 (0) 285#define ANOMALY_05000183 (0)
286#define ANOMALY_05000233 (0) 286#define ANOMALY_05000233 (0)
287#define ANOMALY_05000234 (0)
287#define ANOMALY_05000273 (0) 288#define ANOMALY_05000273 (0)
288#define ANOMALY_05000311 (0) 289#define ANOMALY_05000311 (0)
289#define ANOMALY_05000353 (1) 290#define ANOMALY_05000353 (1)
@@ -298,5 +299,7 @@
298#define ANOMALY_05000448 (0) 299#define ANOMALY_05000448 (0)
299#define ANOMALY_05000456 (0) 300#define ANOMALY_05000456 (0)
300#define ANOMALY_05000450 (0) 301#define ANOMALY_05000450 (0)
302#define ANOMALY_05000465 (0)
303#define ANOMALY_05000467 (0)
301 304
302#endif 305#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 11:38:41 -0500