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-rw-r--r--arch/blackfin/mach-bf561/head.S136
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diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
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1/*
2 * File: arch/blackfin/mach-bf561/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author:
5 *
6 * Created:
7 * Description: BF561 startup file
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/clocks.h>
35#include <mach/mem_init.h>
36#endif
37
38.section .l1.text
39#ifdef CONFIG_BFIN_KERNEL_CLOCK
40ENTRY(_start_dma_code)
41 p0.h = hi(SICA_IWR0);
42 p0.l = lo(SICA_IWR0);
43 r0.l = 0x1;
44 [p0] = r0;
45 SSYNC;
46
47 /*
48 * Set PLL_CTL
49 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
50 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
51 * - [7] = output delay (add 200ps of delay to mem signals)
52 * - [6] = input delay (add 200ps of input delay to mem signals)
53 * - [5] = PDWN : 1=All Clocks off
54 * - [3] = STOPCK : 1=Core Clock off
55 * - [1] = PLL_OFF : 1=Disable Power to PLL
56 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
57 * all other bits set to zero
58 */
59
60 p0.h = hi(PLL_LOCKCNT);
61 p0.l = lo(PLL_LOCKCNT);
62 r0 = 0x300(Z);
63 w[p0] = r0.l;
64 ssync;
65
66 P2.H = hi(EBIU_SDGCTL);
67 P2.L = lo(EBIU_SDGCTL);
68 R0 = [P2];
69 BITSET (R0, 24);
70 [P2] = R0;
71 SSYNC;
72
73 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
74 r0 = r0 << 9; /* Shift it over, */
75 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
76 r0 = r1 | r0;
77 r1 = PLL_BYPASS; /* Bypass the PLL? */
78 r1 = r1 << 8; /* Shift it over */
79 r0 = r1 | r0; /* add them all together */
80#ifdef ANOMALY_05000265
81 BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
82#endif
83
84 p0.h = hi(PLL_CTL);
85 p0.l = lo(PLL_CTL); /* Load the address */
86 cli r2; /* Disable interrupts */
87 ssync;
88 w[p0] = r0.l; /* Set the value */
89 idle; /* Wait for the PLL to stablize */
90 sti r2; /* Enable interrupts */
91
92.Lcheck_again:
93 p0.h = hi(PLL_STAT);
94 p0.l = lo(PLL_STAT);
95 R0 = W[P0](Z);
96 CC = BITTST(R0,5);
97 if ! CC jump .Lcheck_again;
98
99 /* Configure SCLK & CCLK Dividers */
100 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
101 p0.h = hi(PLL_DIV);
102 p0.l = lo(PLL_DIV);
103 w[p0] = r0.l;
104 ssync;
105
106 p0.l = lo(EBIU_SDRRC);
107 p0.h = hi(EBIU_SDRRC);
108 r0 = mem_SDRRC;
109 w[p0] = r0.l;
110 ssync;
111
112 P2.H = hi(EBIU_SDGCTL);
113 P2.L = lo(EBIU_SDGCTL);
114 R0 = [P2];
115 BITCLR (R0, 24);
116 p0.h = hi(EBIU_SDSTAT);
117 p0.l = lo(EBIU_SDSTAT);
118 r2.l = w[p0];
119 cc = bittst(r2,3);
120 if !cc jump .Lskip;
121 NOP;
122 BITSET (R0, 23);
123.Lskip:
124 [P2] = R0;
125 SSYNC;
126
127 R0.L = lo(mem_SDGCTL);
128 R0.H = hi(mem_SDGCTL);
129 R1 = [p2];
130 R1 = R1 | R0;
131 [P2] = R1;
132 SSYNC;
133
134 RTS;
135ENDPROC(_start_dma_code)
136#endif /* CONFIG_BFIN_KERNEL_CLOCK */