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-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h20
1 files changed, 15 insertions, 5 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index c510ae688e28..18a4cd24f673 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -18,7 +18,7 @@
18# error will not work on BF548 silicon version 0.0, or 0.1 18# error will not work on BF548 silicon version 0.0, or 0.1
19#endif 19#endif
20 20
21/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
22#define ANOMALY_05000074 (1) 22#define ANOMALY_05000074 (1)
23/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 23/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
24#define ANOMALY_05000119 (1) 24#define ANOMALY_05000119 (1)
@@ -30,17 +30,17 @@
30#define ANOMALY_05000265 (1) 30#define ANOMALY_05000265 (1)
31/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 31/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
32#define ANOMALY_05000272 (1) 32#define ANOMALY_05000272 (1)
33/* False Hardware Error Exception When ISR Context Is Not Restored */ 33/* False Hardware Error Exception when ISR Context Is Not Restored */
34#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) 34#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
35/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 35/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
36#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) 36#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
37/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 37/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
38#define ANOMALY_05000310 (1) 38#define ANOMALY_05000310 (1)
39/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 39/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
40#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) 40#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
41/* TWI Slave Boot Mode Is Not Functional */ 41/* TWI Slave Boot Mode Is Not Functional */
42#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) 42#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
43/* External FIFO Boot Mode Is Not Functional */ 43/* FIFO Boot Mode Not Functional */
44#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) 44#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
45/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ 45/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
46#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) 46#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
@@ -178,8 +178,12 @@
178#define ANOMALY_05000450 (1) 178#define ANOMALY_05000450 (1)
179/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 179/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
180#define ANOMALY_05000456 (__SILICON_REVISION__ < 3) 180#define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
181/* False Hardware Error when RETI points to invalid memory */ 181/* False Hardware Error when RETI Points to Invalid Memory */
182#define ANOMALY_05000461 (1) 182#define ANOMALY_05000461 (1)
183/* USB Rx DMA hang */
184#define ANOMALY_05000465 (1)
185/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
186#define ANOMALY_05000467 (1)
183 187
184/* Anomalies that don't exist on this proc */ 188/* Anomalies that don't exist on this proc */
185#define ANOMALY_05000099 (0) 189#define ANOMALY_05000099 (0)
@@ -189,30 +193,36 @@
189#define ANOMALY_05000158 (0) 193#define ANOMALY_05000158 (0)
190#define ANOMALY_05000171 (0) 194#define ANOMALY_05000171 (0)
191#define ANOMALY_05000179 (0) 195#define ANOMALY_05000179 (0)
196#define ANOMALY_05000182 (0)
192#define ANOMALY_05000183 (0) 197#define ANOMALY_05000183 (0)
193#define ANOMALY_05000198 (0) 198#define ANOMALY_05000198 (0)
199#define ANOMALY_05000202 (0)
194#define ANOMALY_05000215 (0) 200#define ANOMALY_05000215 (0)
195#define ANOMALY_05000220 (0) 201#define ANOMALY_05000220 (0)
196#define ANOMALY_05000227 (0) 202#define ANOMALY_05000227 (0)
197#define ANOMALY_05000230 (0) 203#define ANOMALY_05000230 (0)
198#define ANOMALY_05000231 (0) 204#define ANOMALY_05000231 (0)
199#define ANOMALY_05000233 (0) 205#define ANOMALY_05000233 (0)
206#define ANOMALY_05000234 (0)
200#define ANOMALY_05000242 (0) 207#define ANOMALY_05000242 (0)
201#define ANOMALY_05000244 (0) 208#define ANOMALY_05000244 (0)
202#define ANOMALY_05000248 (0) 209#define ANOMALY_05000248 (0)
203#define ANOMALY_05000250 (0) 210#define ANOMALY_05000250 (0)
204#define ANOMALY_05000254 (0) 211#define ANOMALY_05000254 (0)
212#define ANOMALY_05000257 (0)
205#define ANOMALY_05000261 (0) 213#define ANOMALY_05000261 (0)
206#define ANOMALY_05000263 (0) 214#define ANOMALY_05000263 (0)
207#define ANOMALY_05000266 (0) 215#define ANOMALY_05000266 (0)
208#define ANOMALY_05000273 (0) 216#define ANOMALY_05000273 (0)
209#define ANOMALY_05000274 (0) 217#define ANOMALY_05000274 (0)
210#define ANOMALY_05000278 (0) 218#define ANOMALY_05000278 (0)
219#define ANOMALY_05000283 (0)
211#define ANOMALY_05000287 (0) 220#define ANOMALY_05000287 (0)
212#define ANOMALY_05000301 (0) 221#define ANOMALY_05000301 (0)
213#define ANOMALY_05000305 (0) 222#define ANOMALY_05000305 (0)
214#define ANOMALY_05000307 (0) 223#define ANOMALY_05000307 (0)
215#define ANOMALY_05000311 (0) 224#define ANOMALY_05000311 (0)
225#define ANOMALY_05000315 (0)
216#define ANOMALY_05000323 (0) 226#define ANOMALY_05000323 (0)
217#define ANOMALY_05000362 (1) 227#define ANOMALY_05000362 (1)
218#define ANOMALY_05000363 (0) 228#define ANOMALY_05000363 (0)