5 files changed, 45 insertions, 104 deletions

diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index f5a3c30a41bd..e565aae11d72 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -291,6 +291,8 @@ static struct platform_device bfin_sir3_device = {
 #endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#include <linux/smsc911x.h>
+
 static struct resource smsc911x_resources[] = {
         {
                 .name = "smsc911x-memory",
@@ -304,11 +306,22 @@ static struct resource smsc911x_resources[] = {
                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
+
+static struct smsc911x_platform_config smsc911x_config = {
+        .flags = SMSC911X_USE_16BIT,
+        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .phy_interface = PHY_INTERFACE_MODE_MII,
+};
+
 static struct platform_device smsc911x_device = {
         .name = "smsc911x",
         .id = 0,
         .num_resources = ARRAY_SIZE(smsc911x_resources),
         .resource = smsc911x_resources,
+        .dev = {
+                .platform_data = &smsc911x_config,
+        },
 };
 #endif
 
@@ -473,7 +486,7 @@ static struct mtd_partition para_partitions[] = {
                 .offset     = 0,
         }, {
                 .name       = "linux kernel(nor)",
-                .size       = 0x400000,
+                .size       = 0x100000,
                 .offset     = MTDPART_OFS_APPEND,
         }, {
                 .name       = "file system(nor)",
@@ -642,7 +655,7 @@ static struct resource bfin_spi1_resource[] = {
 
 /* SPI controller data */
 static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
-        .num_chipselect = 8,
+        .num_chipselect = 3,
         .enable_dma = 1,  /* master has the ability to do dma transfer */
         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 };
@@ -658,7 +671,7 @@ static struct platform_device bf54x_spi_master0 = {
 };
 
 static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
-        .num_chipselect = 8,
+        .num_chipselect = 3,
         .enable_dma = 1,  /* master has the ability to do dma transfer */
         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
 };
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index dc0dd9b2bcef..c66f3801274f 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -99,8 +99,8 @@ static struct platform_device bfin_isp1760_device = {
 #include <mach/bf54x-lq043.h>
 
 static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
-        .width =        480,
-        .height =       272,
+        .width =        95,
+        .height =       54,
         .xres =         {480, 480, 480},
         .yres =         {272, 272, 272},
         .bpp =          {24, 24, 24},
@@ -702,7 +702,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_SND_BLACKFIN_AD1836) \
         || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
         {
-                .modalias = "ad1836-spi",
+                .modalias = "ad1836",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 1,
                 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
@@ -783,7 +783,7 @@ static struct resource bfin_spi1_resource[] = {
 
 /* SPI controller data */
 static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
-        .num_chipselect = 8,
+        .num_chipselect = 3,
         .enable_dma = 1,  /* master has the ability to do dma transfer */
         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 };
@@ -799,7 +799,7 @@ static struct platform_device bf54x_spi_master0 = {
 };
 
 static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
-        .num_chipselect = 8,
+        .num_chipselect = 3,
         .enable_dma = 1,  /* master has the ability to do dma transfer */
         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
 };
@@ -869,7 +869,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
                 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
         },
 #endif
-#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
+#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
         {
                 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                 .irq = 212,
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
index 535980652bf6..d9239bc05dd4 100644
--- a/arch/blackfin/mach-bf548/dma.c
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -91,16 +91,16 @@ int channel2irq(unsigned int channel)
                 ret_irq = IRQ_SPI1;
                 break;
         case CH_UART0_RX:
-                ret_irq = IRQ_UART_RX;
+                ret_irq = IRQ_UART0_RX;
                 break;
         case CH_UART0_TX:
-                ret_irq = IRQ_UART_TX;
+                ret_irq = IRQ_UART0_TX;
                 break;
         case CH_UART1_RX:
-                ret_irq = IRQ_UART_RX;
+                ret_irq = IRQ_UART1_RX;
                 break;
         case CH_UART1_TX:
-                ret_irq = IRQ_UART_TX;
+                ret_irq = IRQ_UART1_TX;
                 break;
         case CH_EPPI0:
                 ret_irq = IRQ_EPPI0;
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index cd040fe0bc5c..52b116ae522a 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -7,7 +7,7 @@
  */
 
 /* This file should be up to date with:
- *  - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ *  - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -162,6 +162,8 @@
 #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
 /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
 #define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
+/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
+#define ANOMALY_05000434 (1)
 /* OTP Write Accesses Not Supported */
 #define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
@@ -176,12 +178,26 @@
 #define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
 /* USB DMA Mode 1 Short Packet Data Corruption */
 #define ANOMALY_05000450 (1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
+#define ANOMALY_05000456 (1)
+/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
+#define ANOMALY_05000457 (1)
+/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
+#define ANOMALY_05000460 (1)
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* USB DMA RX Data Corruption */
+#define ANOMALY_05000463 (1)
+/* USB TX DMA Hang */
+#define ANOMALY_05000464 (1)
 /* USB Rx DMA hang */
 #define ANOMALY_05000465 (1)
+/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
+#define ANOMALY_05000466 (1)
 /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
 #define ANOMALY_05000467 (1)
 
@@ -230,6 +246,7 @@
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
 #define ANOMALY_05000400 (0)
+#define ANOMALY_05000402 (0)
 #define ANOMALY_05000412 (0)
 #define ANOMALY_05000432 (0)
 #define ANOMALY_05000435 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 6b97396d817f..318667b2f036 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -72,97 +72,8 @@
 #include "cdefBF549.h"
 #endif
 
-/* UART 1*/
-#define bfin_read_UART_THR()            bfin_read_UART1_THR()
-#define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
-#define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
-#define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
-#define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
-#define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
-#define bfin_read_UART_IER()            bfin_read_UART1_IER()
-#define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
-#define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
-#define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
-#define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
-#define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
-#define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
-#define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
-#define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
-#define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
-#define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
-#define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
-#define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
-#define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
-#define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
-#define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
-
 #endif
 
-/* MAP used DEFINES from BF533 to BF54x - so we don't need to change 
- * them in the driver, kernel, etc. */
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-
-/* UART 0*/
-
-/* DMA Channel */
-#define bfin_read_CH_UART_RX()          bfin_read_CH_UART1_RX()
-#define bfin_write_CH_UART_RX(val)      bfin_write_CH_UART1_RX(val)
-#define bfin_read_CH_UART_TX()          bfin_read_CH_UART1_TX()
-#define bfin_write_CH_UART_TX(val)      bfin_write_CH_UART1_TX(val)
-#define CH_UART_RX                      CH_UART1_RX
-#define CH_UART_TX                      CH_UART1_TX
-
-/* System Interrupt Controller */
-#define bfin_read_IRQ_UART_RX()         bfin_read_IRQ_UART1_RX()
-#define bfin_write_IRQ_UART_RX(val)     bfin_write_IRQ_UART1_RX(val)
-#define bfin_read_IRQ_UART_TX()         bfin_read_IRQ_UART1_TX()
-#define bfin_write_IRQ_UART_TX(val)     bfin_write_IRQ_UART1_TX(val)
-#define bfin_read_IRQ_UART_ERROR()      bfin_read_IRQ_UART1_ERROR()
-#define bfin_write_IRQ_UART_ERROR(val)  bfin_write_IRQ_UART1_ERROR(val)
-#define IRQ_UART_RX                     IRQ_UART1_RX
-#define IRQ_UART_TX                     IRQ_UART1_TX
-#define IRQ_UART_ERROR                  IRQ_UART1_ERROR
-
-/* MMR Registers*/
-#define bfin_read_UART_THR()            bfin_read_UART1_THR()
-#define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
-#define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
-#define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
-#define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
-#define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
-#define bfin_read_UART_IER()            bfin_read_UART1_IER()
-#define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
-#define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
-#define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
-#define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
-#define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
-#define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
-#define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
-#define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
-#define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
-#define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
-#define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
-#define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
-#define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
-#define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
-#define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
-
-#define BFIN_UART_THR                   UART1_THR
-#define BFIN_UART_RBR                   UART1_RBR
-#define BFIN_UART_DLL                   UART1_DLL
-#define BFIN_UART_IER                   UART1_IER
-#define BFIN_UART_DLH                   UART1_DLH
-#define BFIN_UART_IIR                   UART1_IIR
-#define BFIN_UART_LCR                   UART1_LCR
-#define BFIN_UART_MCR                   UART1_MCR
-#define BFIN_UART_LSR                   UART1_LSR
-#define BFIN_UART_SCR                   UART1_SCR
-#define BFIN_UART_GCTL                  UART1_GCTL
-
 #define BFIN_UART_NR_PORTS      4
 
 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */