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-rw-r--r--arch/blackfin/mach-bf548/Kconfig2
-rw-r--r--arch/blackfin/mach-bf548/Makefile2
-rw-r--r--arch/blackfin/mach-bf548/boards/cm_bf548.c166
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c156
-rw-r--r--arch/blackfin/mach-bf548/dma.c2
-rw-r--r--arch/blackfin/mach-bf548/head.S158
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h5
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bf548.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_sir.h166
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h114
-rw-r--r--arch/blackfin/mach-bf548/include/mach/dma.h32
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/mem_init.h255
-rw-r--r--arch/blackfin/mach-bf548/include/mach/mem_map.h6
15 files changed, 353 insertions, 717 deletions
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index 1bfcd8f646ab..dcf657159051 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -250,7 +250,7 @@ config IRQ_OTPSEC
250 default 11 250 default 11
251config IRQ_TIMER0 251config IRQ_TIMER0
252 int "IRQ_TIMER0" 252 int "IRQ_TIMER0"
253 default 11 253 default 8
254config IRQ_TIMER1 254config IRQ_TIMER1
255 int "IRQ_TIMER1" 255 int "IRQ_TIMER1"
256 default 11 256 default 11
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
index 68e5478e95a9..56994b675f9c 100644
--- a/arch/blackfin/mach-bf548/Makefile
+++ b/arch/blackfin/mach-bf548/Makefile
@@ -2,6 +2,4 @@
2# arch/blackfin/mach-bf537/Makefile 2# arch/blackfin/mach-bf537/Makefile
3# 3#
4 4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o 5obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 24192aaa9275..f53ad682530b 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -32,6 +32,7 @@
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h> 33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h> 34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
35#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 37#include <linux/spi/flash.h>
37#include <linux/irq.h> 38#include <linux/irq.h>
@@ -42,6 +43,7 @@
42#include <asm/gpio.h> 43#include <asm/gpio.h>
43#include <asm/nand.h> 44#include <asm/nand.h>
44#include <asm/portmux.h> 45#include <asm/portmux.h>
46#include <asm/bfin_sdh.h>
45#include <mach/bf54x_keys.h> 47#include <mach/bf54x_keys.h>
46#include <asm/dpmc.h> 48#include <asm/dpmc.h>
47#include <linux/input.h> 49#include <linux/input.h>
@@ -186,44 +188,107 @@ static struct platform_device bfin_uart_device = {
186#endif 188#endif
187 189
188#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 190#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
189static struct resource bfin_sir_resources[] = {
190#ifdef CONFIG_BFIN_SIR0 191#ifdef CONFIG_BFIN_SIR0
192static struct resource bfin_sir0_resources[] = {
191 { 193 {
192 .start = 0xFFC00400, 194 .start = 0xFFC00400,
193 .end = 0xFFC004FF, 195 .end = 0xFFC004FF,
194 .flags = IORESOURCE_MEM, 196 .flags = IORESOURCE_MEM,
195 }, 197 },
198 {
199 .start = IRQ_UART0_RX,
200 .end = IRQ_UART0_RX+1,
201 .flags = IORESOURCE_IRQ,
202 },
203 {
204 .start = CH_UART0_RX,
205 .end = CH_UART0_RX+1,
206 .flags = IORESOURCE_DMA,
207 },
208};
209static struct platform_device bfin_sir0_device = {
210 .name = "bfin_sir",
211 .id = 0,
212 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
213 .resource = bfin_sir0_resources,
214};
196#endif 215#endif
197#ifdef CONFIG_BFIN_SIR1 216#ifdef CONFIG_BFIN_SIR1
217static struct resource bfin_sir1_resources[] = {
198 { 218 {
199 .start = 0xFFC02000, 219 .start = 0xFFC02000,
200 .end = 0xFFC020FF, 220 .end = 0xFFC020FF,
201 .flags = IORESOURCE_MEM, 221 .flags = IORESOURCE_MEM,
202 }, 222 },
223 {
224 .start = IRQ_UART1_RX,
225 .end = IRQ_UART1_RX+1,
226 .flags = IORESOURCE_IRQ,
227 },
228 {
229 .start = CH_UART1_RX,
230 .end = CH_UART1_RX+1,
231 .flags = IORESOURCE_DMA,
232 },
233};
234static struct platform_device bfin_sir1_device = {
235 .name = "bfin_sir",
236 .id = 1,
237 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
238 .resource = bfin_sir1_resources,
239};
203#endif 240#endif
204#ifdef CONFIG_BFIN_SIR2 241#ifdef CONFIG_BFIN_SIR2
242static struct resource bfin_sir2_resources[] = {
205 { 243 {
206 .start = 0xFFC02100, 244 .start = 0xFFC02100,
207 .end = 0xFFC021FF, 245 .end = 0xFFC021FF,
208 .flags = IORESOURCE_MEM, 246 .flags = IORESOURCE_MEM,
209 }, 247 },
248 {
249 .start = IRQ_UART2_RX,
250 .end = IRQ_UART2_RX+1,
251 .flags = IORESOURCE_IRQ,
252 },
253 {
254 .start = CH_UART2_RX,
255 .end = CH_UART2_RX+1,
256 .flags = IORESOURCE_DMA,
257 },
258};
259static struct platform_device bfin_sir2_device = {
260 .name = "bfin_sir",
261 .id = 2,
262 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
263 .resource = bfin_sir2_resources,
264};
210#endif 265#endif
211#ifdef CONFIG_BFIN_SIR3 266#ifdef CONFIG_BFIN_SIR3
267static struct resource bfin_sir3_resources[] = {
212 { 268 {
213 .start = 0xFFC03100, 269 .start = 0xFFC03100,
214 .end = 0xFFC031FF, 270 .end = 0xFFC031FF,
215 .flags = IORESOURCE_MEM, 271 .flags = IORESOURCE_MEM,
216 }, 272 },
217#endif 273 {
274 .start = IRQ_UART3_RX,
275 .end = IRQ_UART3_RX+1,
276 .flags = IORESOURCE_IRQ,
277 },
278 {
279 .start = CH_UART3_RX,
280 .end = CH_UART3_RX+1,
281 .flags = IORESOURCE_DMA,
282 },
218}; 283};
219 284static struct platform_device bfin_sir3_device = {
220static struct platform_device bfin_sir_device = {
221 .name = "bfin_sir", 285 .name = "bfin_sir",
222 .id = 0, 286 .id = 3,
223 .num_resources = ARRAY_SIZE(bfin_sir_resources), 287 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
224 .resource = bfin_sir_resources, 288 .resource = bfin_sir3_resources,
225}; 289};
226#endif 290#endif
291#endif
227 292
228#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) 293#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
229static struct resource smsc911x_resources[] = { 294static struct resource smsc911x_resources[] = {
@@ -271,8 +336,8 @@ static struct musb_hdrc_config musb_config = {
271 .dyn_fifo = 0, 336 .dyn_fifo = 0,
272 .soft_con = 1, 337 .soft_con = 1,
273 .dma = 1, 338 .dma = 1,
274 .num_eps = 7, 339 .num_eps = 8,
275 .dma_channels = 7, 340 .dma_channels = 8,
276 .gpio_vrsel = GPIO_PH6, 341 .gpio_vrsel = GPIO_PH6,
277}; 342};
278 343
@@ -302,6 +367,19 @@ static struct platform_device musb_device = {
302}; 367};
303#endif 368#endif
304 369
370static struct resource bfin_gpios_resources = {
371 .start = 0,
372 .end = MAX_BLACKFIN_GPIOS - 1,
373 .flags = IORESOURCE_IRQ,
374};
375
376static struct platform_device bfin_gpios_device = {
377 .name = "simple-gpio",
378 .id = -1,
379 .num_resources = 1,
380 .resource = &bfin_gpios_resources,
381};
382
305#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) 383#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
306static struct resource bfin_atapi_resources[] = { 384static struct resource bfin_atapi_resources[] = {
307 { 385 {
@@ -372,9 +450,58 @@ static struct platform_device bf5xx_nand_device = {
372#endif 450#endif
373 451
374#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) 452#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
453static struct bfin_sd_host bfin_sdh_data = {
454 .dma_chan = CH_SDH,
455 .irq_int0 = IRQ_SDH_MASK0,
456 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
457};
458
375static struct platform_device bf54x_sdh_device = { 459static struct platform_device bf54x_sdh_device = {
376 .name = "bfin-sdh", 460 .name = "bfin-sdh",
377 .id = 0, 461 .id = 0,
462 .dev = {
463 .platform_data = &bfin_sdh_data,
464 },
465};
466#endif
467
468#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
469static struct mtd_partition para_partitions[] = {
470 {
471 .name = "bootloader(nor)",
472 .size = 0x40000,
473 .offset = 0,
474 }, {
475 .name = "linux kernel(nor)",
476 .size = 0x400000,
477 .offset = MTDPART_OFS_APPEND,
478 }, {
479 .name = "file system(nor)",
480 .size = MTDPART_SIZ_FULL,
481 .offset = MTDPART_OFS_APPEND,
482 }
483};
484
485static struct physmap_flash_data para_flash_data = {
486 .width = 2,
487 .parts = para_partitions,
488 .nr_parts = ARRAY_SIZE(para_partitions),
489};
490
491static struct resource para_flash_resource = {
492 .start = 0x20000000,
493 .end = 0x207fffff,
494 .flags = IORESOURCE_MEM,
495};
496
497static struct platform_device para_flash_device = {
498 .name = "physmap-flash",
499 .id = 0,
500 .dev = {
501 .platform_data = &para_flash_data,
502 },
503 .num_resources = 1,
504 .resource = &para_flash_resource,
378}; 505};
379#endif 506#endif
380 507
@@ -642,7 +769,18 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
642#endif 769#endif
643 770
644#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 771#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
645 &bfin_sir_device, 772#ifdef CONFIG_BFIN_SIR0
773 &bfin_sir0_device,
774#endif
775#ifdef CONFIG_BFIN_SIR1
776 &bfin_sir1_device,
777#endif
778#ifdef CONFIG_BFIN_SIR2
779 &bfin_sir2_device,
780#endif
781#ifdef CONFIG_BFIN_SIR3
782 &bfin_sir3_device,
783#endif
646#endif 784#endif
647 785
648#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) 786#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
@@ -679,7 +817,7 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
679#endif 817#endif
680 818
681#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 819#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
682/* &i2c_bfin_twi0_device, */ 820 &i2c_bfin_twi0_device,
683#if !defined(CONFIG_BF542) 821#if !defined(CONFIG_BF542)
684 &i2c_bfin_twi1_device, 822 &i2c_bfin_twi1_device,
685#endif 823#endif
@@ -688,6 +826,12 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
688#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 826#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
689 &bfin_device_gpiokeys, 827 &bfin_device_gpiokeys,
690#endif 828#endif
829
830#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
831 &para_flash_device,
832#endif
833
834 &bfin_gpios_device,
691}; 835};
692 836
693static int __init cm_bf548_init(void) 837static int __init cm_bf548_init(void)
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 5288187a3ace..309c16014cae 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -45,6 +45,7 @@
45#include <asm/nand.h> 45#include <asm/nand.h>
46#include <asm/dpmc.h> 46#include <asm/dpmc.h>
47#include <asm/portmux.h> 47#include <asm/portmux.h>
48#include <asm/bfin_sdh.h>
48#include <mach/bf54x_keys.h> 49#include <mach/bf54x_keys.h>
49#include <linux/input.h> 50#include <linux/input.h>
50#include <linux/spi/ad7877.h> 51#include <linux/spi/ad7877.h>
@@ -52,16 +53,16 @@
52/* 53/*
53 * Name the Board for the /proc/cpuinfo 54 * Name the Board for the /proc/cpuinfo
54 */ 55 */
55const char bfin_board_name[] = "ADSP-BF548-EZKIT"; 56const char bfin_board_name[] = "ADI BF548-EZKIT";
56 57
57/* 58/*
58 * Driver needs to know address, irq and flag pin. 59 * Driver needs to know address, irq and flag pin.
59 */ 60 */
60 61
61#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) 62#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
62static struct resource bfin_isp1761_resources[] = { 63#include <linux/usb/isp1760.h>
64static struct resource bfin_isp1760_resources[] = {
63 [0] = { 65 [0] = {
64 .name = "isp1761-regs",
65 .start = 0x2C0C0000, 66 .start = 0x2C0C0000,
66 .end = 0x2C0C0000 + 0xfffff, 67 .end = 0x2C0C0000 + 0xfffff,
67 .flags = IORESOURCE_MEM, 68 .flags = IORESOURCE_MEM,
@@ -73,32 +74,25 @@ static struct resource bfin_isp1761_resources[] = {
73 }, 74 },
74}; 75};
75 76
76static struct platform_device bfin_isp1761_device = { 77static struct isp1760_platform_data isp1760_priv = {
77 .name = "isp1761", 78 .is_isp1761 = 0,
78 .id = 0, 79 .port1_disable = 0,
79 .num_resources = ARRAY_SIZE(bfin_isp1761_resources), 80 .bus_width_16 = 1,
80 .resource = bfin_isp1761_resources, 81 .port1_otg = 0,
82 .analog_oc = 0,
83 .dack_polarity_high = 0,
84 .dreq_polarity_high = 0,
81}; 85};
82 86
83static struct platform_device *bfin_isp1761_devices[] = { 87static struct platform_device bfin_isp1760_device = {
84 &bfin_isp1761_device, 88 .name = "isp1760-hcd",
89 .id = 0,
90 .dev = {
91 .platform_data = &isp1760_priv,
92 },
93 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
94 .resource = bfin_isp1760_resources,
85}; 95};
86
87int __init bfin_isp1761_init(void)
88{
89 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
90
91 printk(KERN_INFO "%s(): registering device resources\n", __func__);
92 set_irq_type(bfin_isp1761_resources[1].start, IRQF_TRIGGER_FALLING);
93
94 return platform_add_devices(bfin_isp1761_devices, num_devices);
95}
96
97void __exit bfin_isp1761_exit(void)
98{
99 platform_device_unregister(&bfin_isp1761_device);
100}
101arch_initcall(bfin_isp1761_init);
102#endif 96#endif
103 97
104#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) 98#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
@@ -262,44 +256,107 @@ static struct platform_device bfin_uart_device = {
262#endif 256#endif
263 257
264#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 258#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
265static struct resource bfin_sir_resources[] = {
266#ifdef CONFIG_BFIN_SIR0 259#ifdef CONFIG_BFIN_SIR0
260static struct resource bfin_sir0_resources[] = {
267 { 261 {
268 .start = 0xFFC00400, 262 .start = 0xFFC00400,
269 .end = 0xFFC004FF, 263 .end = 0xFFC004FF,
270 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
271 }, 265 },
266 {
267 .start = IRQ_UART0_RX,
268 .end = IRQ_UART0_RX+1,
269 .flags = IORESOURCE_IRQ,
270 },
271 {
272 .start = CH_UART0_RX,
273 .end = CH_UART0_RX+1,
274 .flags = IORESOURCE_DMA,
275 },
276};
277static struct platform_device bfin_sir0_device = {
278 .name = "bfin_sir",
279 .id = 0,
280 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
281 .resource = bfin_sir0_resources,
282};
272#endif 283#endif
273#ifdef CONFIG_BFIN_SIR1 284#ifdef CONFIG_BFIN_SIR1
285static struct resource bfin_sir1_resources[] = {
274 { 286 {
275 .start = 0xFFC02000, 287 .start = 0xFFC02000,
276 .end = 0xFFC020FF, 288 .end = 0xFFC020FF,
277 .flags = IORESOURCE_MEM, 289 .flags = IORESOURCE_MEM,
278 }, 290 },
291 {
292 .start = IRQ_UART1_RX,
293 .end = IRQ_UART1_RX+1,
294 .flags = IORESOURCE_IRQ,
295 },
296 {
297 .start = CH_UART1_RX,
298 .end = CH_UART1_RX+1,
299 .flags = IORESOURCE_DMA,
300 },
301};
302static struct platform_device bfin_sir1_device = {
303 .name = "bfin_sir",
304 .id = 1,
305 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
306 .resource = bfin_sir1_resources,
307};
279#endif 308#endif
280#ifdef CONFIG_BFIN_SIR2 309#ifdef CONFIG_BFIN_SIR2
310static struct resource bfin_sir2_resources[] = {
281 { 311 {
282 .start = 0xFFC02100, 312 .start = 0xFFC02100,
283 .end = 0xFFC021FF, 313 .end = 0xFFC021FF,
284 .flags = IORESOURCE_MEM, 314 .flags = IORESOURCE_MEM,
285 }, 315 },
316 {
317 .start = IRQ_UART2_RX,
318 .end = IRQ_UART2_RX+1,
319 .flags = IORESOURCE_IRQ,
320 },
321 {
322 .start = CH_UART2_RX,
323 .end = CH_UART2_RX+1,
324 .flags = IORESOURCE_DMA,
325 },
326};
327static struct platform_device bfin_sir2_device = {
328 .name = "bfin_sir",
329 .id = 2,
330 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
331 .resource = bfin_sir2_resources,
332};
286#endif 333#endif
287#ifdef CONFIG_BFIN_SIR3 334#ifdef CONFIG_BFIN_SIR3
335static struct resource bfin_sir3_resources[] = {
288 { 336 {
289 .start = 0xFFC03100, 337 .start = 0xFFC03100,
290 .end = 0xFFC031FF, 338 .end = 0xFFC031FF,
291 .flags = IORESOURCE_MEM, 339 .flags = IORESOURCE_MEM,
292 }, 340 },
293#endif 341 {
342 .start = IRQ_UART3_RX,
343 .end = IRQ_UART3_RX+1,
344 .flags = IORESOURCE_IRQ,
345 },
346 {
347 .start = CH_UART3_RX,
348 .end = CH_UART3_RX+1,
349 .flags = IORESOURCE_DMA,
350 },
294}; 351};
295 352static struct platform_device bfin_sir3_device = {
296static struct platform_device bfin_sir_device = {
297 .name = "bfin_sir", 353 .name = "bfin_sir",
298 .id = 0, 354 .id = 3,
299 .num_resources = ARRAY_SIZE(bfin_sir_resources), 355 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
300 .resource = bfin_sir_resources, 356 .resource = bfin_sir3_resources,
301}; 357};
302#endif 358#endif
359#endif
303 360
304#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) 361#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
305static struct resource smsc911x_resources[] = { 362static struct resource smsc911x_resources[] = {
@@ -347,8 +404,8 @@ static struct musb_hdrc_config musb_config = {
347 .dyn_fifo = 0, 404 .dyn_fifo = 0,
348 .soft_con = 1, 405 .soft_con = 1,
349 .dma = 1, 406 .dma = 1,
350 .num_eps = 7, 407 .num_eps = 8,
351 .dma_channels = 7, 408 .dma_channels = 8,
352 .gpio_vrsel = GPIO_PE7, 409 .gpio_vrsel = GPIO_PE7,
353}; 410};
354 411
@@ -448,9 +505,19 @@ static struct platform_device bf5xx_nand_device = {
448#endif 505#endif
449 506
450#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) 507#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
508
509static struct bfin_sd_host bfin_sdh_data = {
510 .dma_chan = CH_SDH,
511 .irq_int0 = IRQ_SDH_MASK0,
512 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
513};
514
451static struct platform_device bf54x_sdh_device = { 515static struct platform_device bf54x_sdh_device = {
452 .name = "bfin-sdh", 516 .name = "bfin-sdh",
453 .id = 0, 517 .id = 0,
518 .dev = {
519 .platform_data = &bfin_sdh_data,
520 },
454}; 521};
455#endif 522#endif
456 523
@@ -589,7 +656,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
589{ 656{
590 .modalias = "ad7877", 657 .modalias = "ad7877",
591 .platform_data = &bfin_ad7877_ts_info, 658 .platform_data = &bfin_ad7877_ts_info,
592 .irq = IRQ_PJ11, /* newer boards (Rev 1.4+) use IRQ_PB4 */ 659 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
593 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 660 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
594 .bus_num = 0, 661 .bus_num = 0,
595 .chip_select = 2, 662 .chip_select = 2,
@@ -812,7 +879,18 @@ static struct platform_device *ezkit_devices[] __initdata = {
812#endif 879#endif
813 880
814#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 881#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
815 &bfin_sir_device, 882#ifdef CONFIG_BFIN_SIR0
883 &bfin_sir0_device,
884#endif
885#ifdef CONFIG_BFIN_SIR1
886 &bfin_sir1_device,
887#endif
888#ifdef CONFIG_BFIN_SIR2
889 &bfin_sir2_device,
890#endif
891#ifdef CONFIG_BFIN_SIR3
892 &bfin_sir3_device,
893#endif
816#endif 894#endif
817 895
818#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) 896#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
@@ -827,6 +905,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
827 &musb_device, 905 &musb_device,
828#endif 906#endif
829 907
908#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
909 &bfin_isp1760_device,
910#endif
911
830#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) 912#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
831 &bfin_atapi_device, 913 &bfin_atapi_device,
832#endif 914#endif
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
index 74730eb8ae1b..535980652bf6 100644
--- a/arch/blackfin/mach-bf548/dma.c
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -32,7 +32,7 @@
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/dma.h> 33#include <asm/dma.h>
34 34
35struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { 35struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
36 (struct dma_register *) DMA0_NEXT_DESC_PTR, 36 (struct dma_register *) DMA0_NEXT_DESC_PTR,
37 (struct dma_register *) DMA1_NEXT_DESC_PTR, 37 (struct dma_register *) DMA1_NEXT_DESC_PTR,
38 (struct dma_register *) DMA2_NEXT_DESC_PTR, 38 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
deleted file mode 100644
index 93b361dff27b..000000000000
--- a/arch/blackfin/mach-bf548/head.S
+++ /dev/null
@@ -1,158 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf548/head.S
3 * Based on: arch/blackfin/mach-bf537/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/clocks.h>
35#include <mach/mem_init.h>
36#endif
37
38.section .l1.text
39#ifdef CONFIG_BFIN_KERNEL_CLOCK
40ENTRY(_start_dma_code)
41
42 /* Enable PHY CLK buffer output */
43 p0.h = hi(VR_CTL);
44 p0.l = lo(VR_CTL);
45 r0.l = w[p0];
46 bitset(r0, 14);
47 w[p0] = r0.l;
48 ssync;
49
50 p0.h = hi(SIC_IWR0);
51 p0.l = lo(SIC_IWR0);
52 r0.l = 0x1;
53 r0.h = 0x0;
54 [p0] = r0;
55 SSYNC;
56
57 /*
58 * Set PLL_CTL
59 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
60 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
61 * - [7] = output delay (add 200ps of delay to mem signals)
62 * - [6] = input delay (add 200ps of input delay to mem signals)
63 * - [5] = PDWN : 1=All Clocks off
64 * - [3] = STOPCK : 1=Core Clock off
65 * - [1] = PLL_OFF : 1=Disable Power to PLL
66 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
67 * all other bits set to zero
68 */
69
70 p0.h = hi(PLL_LOCKCNT);
71 p0.l = lo(PLL_LOCKCNT);
72 r0 = 0x300(Z);
73 w[p0] = r0.l;
74 ssync;
75
76 /* enable self refresh via SRREQ */
77 P2.H = hi(EBIU_RSTCTL);
78 P2.L = lo(EBIU_RSTCTL);
79 R0 = [P2];
80 BITSET (R0, 3);
81 [P2] = R0;
82 SSYNC;
83
84 /* wait for SRACK bit to be set */
85.LSRR_MODE:
86 R0 = [P2];
87 CC = BITTST(R0, 4);
88 if !CC JUMP .LSRR_MODE;
89
90 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
91 r0 = r0 << 9; /* Shift it over, */
92 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
93 r0 = r1 | r0;
94 r1 = PLL_BYPASS; /* Bypass the PLL? */
95 r1 = r1 << 8; /* Shift it over */
96 r0 = r1 | r0; /* add them all together */
97#ifdef ANOMALY_05000265
98 BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
99#endif
100
101 p0.h = hi(PLL_CTL);
102 p0.l = lo(PLL_CTL); /* Load the address */
103 cli r2; /* Disable interrupts */
104 ssync;
105 w[p0] = r0.l; /* Set the value */
106 idle; /* Wait for the PLL to stablize */
107 sti r2; /* Enable interrupts */
108
109.Lcheck_again:
110 p0.h = hi(PLL_STAT);
111 p0.l = lo(PLL_STAT);
112 R0 = W[P0](Z);
113 CC = BITTST(R0,5);
114 if ! CC jump .Lcheck_again;
115
116 /* Configure SCLK & CCLK Dividers */
117 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
118 p0.h = hi(PLL_DIV);
119 p0.l = lo(PLL_DIV);
120 w[p0] = r0.l;
121 ssync;
122
123 /* disable self refresh by clearing SRREQ */
124 P2.H = hi(EBIU_RSTCTL);
125 P2.L = lo(EBIU_RSTCTL);
126 R0 = [P2];
127 CC = BITTST(R0, 0);
128 if CC jump .Lskipddrrst;
129 BITSET (R0, 0);
130.Lskipddrrst:
131 BITCLR (R0, 3);
132 [P2] = R0;
133 SSYNC;
134
135 p0.l = lo(EBIU_DDRCTL0);
136 p0.h = hi(EBIU_DDRCTL0);
137 r0.l = lo(mem_DDRCTL0);
138 r0.h = hi(mem_DDRCTL0);
139 [p0] = r0;
140 ssync;
141
142 p0.l = lo(EBIU_DDRCTL1);
143 p0.h = hi(EBIU_DDRCTL1);
144 r0.l = lo(mem_DDRCTL1);
145 r0.h = hi(mem_DDRCTL1);
146 [p0] = r0;
147 ssync;
148
149 p0.l = lo(EBIU_DDRCTL2);
150 p0.h = hi(EBIU_DDRCTL2);
151 r0.l = lo(mem_DDRCTL2);
152 r0.h = hi(mem_DDRCTL2);
153 [p0] = r0;
154 ssync;
155
156 RTS;
157ENDPROC(_start_dma_code)
158#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 816b09278f62..3b5430999f4f 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -157,6 +157,8 @@
157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) 157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
158/* Software System Reset Corrupts PLL_LOCKCNT Register */ 158/* Software System Reset Corrupts PLL_LOCKCNT Register */
159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) 159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
160/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
161#define ANOMALY_05000443 (1)
160 162
161/* Anomalies that don't exist on this proc */ 163/* Anomalies that don't exist on this proc */
162#define ANOMALY_05000125 (0) 164#define ANOMALY_05000125 (0)
@@ -173,5 +175,8 @@
173#define ANOMALY_05000311 (0) 175#define ANOMALY_05000311 (0)
174#define ANOMALY_05000323 (0) 176#define ANOMALY_05000323 (0)
175#define ANOMALY_05000363 (0) 177#define ANOMALY_05000363 (0)
178#define ANOMALY_05000412 (0)
179#define ANOMALY_05000432 (0)
180#define ANOMALY_05000435 (0)
176 181
177#endif 182#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
index 49f9b403d458..f0e569984810 100644
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ b/arch/blackfin/mach-bf548/include/mach/bf548.h
@@ -122,7 +122,7 @@
122#endif 122#endif
123 123
124#ifndef CPU 124#ifndef CPU
125#error Unknown CPU type - This kernel doesn't seem to be configured properly 125#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
126#endif 126#endif
127 127
128#endif /* __MACH_BF48_H__ */ 128#endif /* __MACH_BF48_H__ */
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h
deleted file mode 100644
index c41f9cf00268..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
21#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
27#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
28#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
29#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
30#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
31#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
32#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
33
34#ifdef CONFIG_SIR_BFIN_DMA
35struct dma_rx_buf {
36 char *buf;
37 int head;
38 int tail;
39 };
40#endif /* CONFIG_SIR_BFIN_DMA */
41
42struct bfin_sir_port {
43 unsigned char __iomem *membase;
44 unsigned int irq;
45 unsigned int lsr;
46 unsigned long clk;
47 struct net_device *dev;
48#ifdef CONFIG_SIR_BFIN_DMA
49 int tx_done;
50 struct dma_rx_buf rx_dma_buf;
51 struct timer_list rx_dma_timer;
52 int rx_dma_nrows;
53#endif /* CONFIG_SIR_BFIN_DMA */
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56};
57
58struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
59
60struct bfin_sir_port_res {
61 unsigned long base_addr;
62 int irq;
63 unsigned int rx_dma_channel;
64 unsigned int tx_dma_channel;
65};
66
67struct bfin_sir_port_res bfin_sir_port_resource[] = {
68#ifdef CONFIG_BFIN_SIR0
69 {
70 0xFFC00400,
71 IRQ_UART0_RX,
72 CH_UART0_RX,
73 CH_UART0_TX,
74 },
75#endif
76#ifdef CONFIG_BFIN_SIR1
77 {
78 0xFFC02000,
79 IRQ_UART1_RX,
80 CH_UART1_RX,
81 CH_UART1_TX,
82 },
83#endif
84#ifdef CONFIG_BFIN_SIR2
85 {
86 0xFFC02100,
87 IRQ_UART2_RX,
88 CH_UART2_RX,
89 CH_UART2_TX,
90 },
91#endif
92#ifdef CONFIG_BFIN_SIR3
93 {
94 0xFFC03100,
95 IRQ_UART3_RX,
96 CH_UART3_RX,
97 CH_UART3_TX,
98 },
99#endif
100};
101
102int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
103
104struct bfin_sir_self {
105 struct bfin_sir_port *sir_port;
106 spinlock_t lock;
107 unsigned int open;
108 int speed;
109 int newspeed;
110
111 struct sk_buff *txskb;
112 struct sk_buff *rxskb;
113 struct net_device_stats stats;
114 struct device *dev;
115 struct irlap_cb *irlap;
116 struct qos_info qos;
117
118 iobuff_t tx_buff;
119 iobuff_t rx_buff;
120
121 struct work_struct work;
122 int mtt;
123};
124
125#define DRIVER_NAME "bfin_sir"
126
127static int bfin_sir_hw_init(void)
128{
129 int ret = -ENODEV;
130#ifdef CONFIG_BFIN_SIR0
131 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
132 if (ret)
133 return ret;
134 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
135 if (ret)
136 return ret;
137#endif
138
139#ifdef CONFIG_BFIN_SIR1
140 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
141 if (ret)
142 return ret;
143 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
144 if (ret)
145 return ret;
146#endif
147
148#ifdef CONFIG_BFIN_SIR2
149 ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
150 if (ret)
151 return ret;
152 ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
153 if (ret)
154 return ret;
155#endif
156
157#ifdef CONFIG_BFIN_SIR3
158 ret = peripheral_request(P_UART3_TX, DRIVER_NAME);
159 if (ret)
160 return ret;
161 ret = peripheral_request(P_UART3_RX, DRIVER_NAME);
162 if (ret)
163 return ret;
164#endif
165 return ret;
166}
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index d6ee74ac0460..0c0e3e2c3c21 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -111,7 +111,7 @@
111 111
112/* UART 0*/ 112/* UART 0*/
113 113
114/* DMA Channnel */ 114/* DMA Channel */
115#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() 115#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
116#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) 116#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
117#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() 117#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index 57ac8cb9b1f6..6e636c418cb0 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -34,7 +34,6 @@
34#include <asm/blackfin.h> 34#include <asm/blackfin.h>
35 35
36#include "defBF54x_base.h" 36#include "defBF54x_base.h"
37#include <asm/system.h>
38 37
39/* ************************************************************** */ 38/* ************************************************************** */
40/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 39/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
@@ -43,63 +42,9 @@
43/* PLL Registers */ 42/* PLL Registers */
44 43
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1, iwr2;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(PLL_CTL, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71 local_irq_restore(flags);
72}
73#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 45#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
74#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 46#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
75#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 47#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
76/* Writing to VR_CTL initiates a PLL relock sequence. */
77static __inline__ void bfin_write_VR_CTL(unsigned int val)
78{
79 unsigned long flags, iwr0, iwr1, iwr2;
80
81 if (val == bfin_read_VR_CTL())
82 return;
83
84 local_irq_save(flags);
85 /* Enable the PLL Wakeup bit in SIC IWR */
86 iwr0 = bfin_read32(SIC_IWR0);
87 iwr1 = bfin_read32(SIC_IWR1);
88 iwr2 = bfin_read32(SIC_IWR2);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
91 bfin_write32(SIC_IWR1, 0);
92 bfin_write32(SIC_IWR2, 0);
93
94 bfin_write16(VR_CTL, val);
95 SSYNC();
96 asm("IDLE;");
97
98 bfin_write32(SIC_IWR0, iwr0);
99 bfin_write32(SIC_IWR1, iwr1);
100 bfin_write32(SIC_IWR2, iwr2);
101 local_irq_restore(flags);
102}
103#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
104#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
105#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -2746,5 +2691,64 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2746#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST 2691#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2747#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST 2692#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2748 2693
2694/* These need to be last due to the cdef/linux inter-dependencies */
2695#include <asm/irq.h>
2696
2697/* Writing to PLL_CTL initiates a PLL relock sequence. */
2698static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2699{
2700 unsigned long flags, iwr0, iwr1, iwr2;
2701
2702 if (val == bfin_read_PLL_CTL())
2703 return;
2704
2705 local_irq_save_hw(flags);
2706 /* Enable the PLL Wakeup bit in SIC IWR */
2707 iwr0 = bfin_read32(SIC_IWR0);
2708 iwr1 = bfin_read32(SIC_IWR1);
2709 iwr2 = bfin_read32(SIC_IWR2);
2710 /* Only allow PPL Wakeup) */
2711 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2712 bfin_write32(SIC_IWR1, 0);
2713 bfin_write32(SIC_IWR2, 0);
2714
2715 bfin_write16(PLL_CTL, val);
2716 SSYNC();
2717 asm("IDLE;");
2718
2719 bfin_write32(SIC_IWR0, iwr0);
2720 bfin_write32(SIC_IWR1, iwr1);
2721 bfin_write32(SIC_IWR2, iwr2);
2722 local_irq_restore_hw(flags);
2723}
2724
2725/* Writing to VR_CTL initiates a PLL relock sequence. */
2726static __inline__ void bfin_write_VR_CTL(unsigned int val)
2727{
2728 unsigned long flags, iwr0, iwr1, iwr2;
2729
2730 if (val == bfin_read_VR_CTL())
2731 return;
2732
2733 local_irq_save_hw(flags);
2734 /* Enable the PLL Wakeup bit in SIC IWR */
2735 iwr0 = bfin_read32(SIC_IWR0);
2736 iwr1 = bfin_read32(SIC_IWR1);
2737 iwr2 = bfin_read32(SIC_IWR2);
2738 /* Only allow PPL Wakeup) */
2739 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2740 bfin_write32(SIC_IWR1, 0);
2741 bfin_write32(SIC_IWR2, 0);
2742
2743 bfin_write16(VR_CTL, val);
2744 SSYNC();
2745 asm("IDLE;");
2746
2747 bfin_write32(SIC_IWR0, iwr0);
2748 bfin_write32(SIC_IWR1, iwr1);
2749 bfin_write32(SIC_IWR2, iwr2);
2750 local_irq_restore_hw(flags);
2751}
2752
2749#endif /* _CDEF_BF54X_H */ 2753#endif /* _CDEF_BF54X_H */
2750 2754
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
index 36a2ef7e7849..a30d242c7398 100644
--- a/arch/blackfin/mach-bf548/include/mach/dma.h
+++ b/arch/blackfin/mach-bf548/include/mach/dma.h
@@ -1,32 +1,8 @@
1/* 1/* mach/dma.h - arch-specific DMA defines
2 * file: include/asm-blackfin/mach-bf548/dma.h
3 * based on:
4 * author:
5 * 2 *
6 * created: 3 * Copyright 2004-2008 Analog Devices Inc.
7 * description:
8 * system mmr register map
9 * rev:
10 * 4 *
11 * modified: 5 * Licensed under the GPL-2 or later.
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */ 6 */
31 7
32#ifndef _MACH_DMA_H_ 8#ifndef _MACH_DMA_H_
@@ -71,6 +47,6 @@
71#define CH_MEM_STREAM3_DEST 30 47#define CH_MEM_STREAM3_DEST 30
72#define CH_MEM_STREAM3_SRC 31 48#define CH_MEM_STREAM3_SRC 31
73 49
74#define MAX_BLACKFIN_DMA_CHANNEL 32 50#define MAX_DMA_CHANNELS 32
75 51
76#endif 52#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index ad380d1f5872..60299a71e090 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -158,7 +158,7 @@ Events (highest priority) EMU 0
158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ 158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ 159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
160 160
161#define SYS_IRQS IRQ_PINT3 161#define SYS_IRQS IRQ_PINT3
162 162
163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) 163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
164#define IRQ_PA0 BFIN_PA_IRQ(0) 164#define IRQ_PA0 BFIN_PA_IRQ(0)
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_init.h b/arch/blackfin/mach-bf548/include/mach/mem_init.h
deleted file mode 100644
index ab0b863eee66..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/mem_init.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
33#define DDR_CLK_HZ(x) (1000*1000*1000/x)
34
35#if (CONFIG_MEM_MT46V32M16_6T)
36#define DDR_SIZE DEVSZ_512
37#define DDR_WIDTH DEVWD_16
38#define DDR_MAX_tCK 13
39
40#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
41#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
42#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
43#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
44#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
45
46#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
47#define DDR_tWTR DDR_TWTR(1)
48#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
49#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
50#endif
51
52#if (CONFIG_MEM_MT46V32M16_5B)
53#define DDR_SIZE DEVSZ_512
54#define DDR_WIDTH DEVWD_16
55#define DDR_MAX_tCK 13
56
57#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
58#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
59#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
60#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
61#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
62
63#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
64#define DDR_tWTR DDR_TWTR(2)
65#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
66#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
67#endif
68
69#if (CONFIG_MEM_GENERIC_BOARD)
70#define DDR_SIZE DEVSZ_512
71#define DDR_WIDTH DEVWD_16
72#define DDR_MAX_tCK 13
73
74#define DDR_tRCD DDR_TRCD(3)
75#define DDR_tWTR DDR_TWTR(2)
76#define DDR_tWR DDR_TWR(2)
77#define DDR_tMRD DDR_TMRD(2)
78#define DDR_tRP DDR_TRP(3)
79#define DDR_tRAS DDR_TRAS(7)
80#define DDR_tRC DDR_TRC(10)
81#define DDR_tRFC DDR_TRFC(12)
82#define DDR_tREFI DDR_TREFI(1288)
83#endif
84
85#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
86# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
87#elif(CONFIG_SCLK_HZ <= 133333333)
88# define DDR_CL CL_2
89#else
90# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
91#endif
92
93
94#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
95#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
96 | DDR_tMRD | DDR_tWR | DDR_tRCD)
97#define mem_DDRCTL2 DDR_CL
98
99
100#if defined CONFIG_CLKIN_HALF
101#define CLKIN_HALF 1
102#else
103#define CLKIN_HALF 0
104#endif
105
106#if defined CONFIG_PLL_BYPASS
107#define PLL_BYPASS 1
108#else
109#define PLL_BYPASS 0
110#endif
111
112/***************************************Currently Not Being Used *********************************/
113#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
114#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
115#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
116#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
117#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
118
119#if (flash_EBIU_AMBCTL_TT > 3)
120#define flash_EBIU_AMBCTL0_TT B0TT_4
121#endif
122#if (flash_EBIU_AMBCTL_TT == 3)
123#define flash_EBIU_AMBCTL0_TT B0TT_3
124#endif
125#if (flash_EBIU_AMBCTL_TT == 2)
126#define flash_EBIU_AMBCTL0_TT B0TT_2
127#endif
128#if (flash_EBIU_AMBCTL_TT < 2)
129#define flash_EBIU_AMBCTL0_TT B0TT_1
130#endif
131
132#if (flash_EBIU_AMBCTL_ST > 3)
133#define flash_EBIU_AMBCTL0_ST B0ST_4
134#endif
135#if (flash_EBIU_AMBCTL_ST == 3)
136#define flash_EBIU_AMBCTL0_ST B0ST_3
137#endif
138#if (flash_EBIU_AMBCTL_ST == 2)
139#define flash_EBIU_AMBCTL0_ST B0ST_2
140#endif
141#if (flash_EBIU_AMBCTL_ST < 2)
142#define flash_EBIU_AMBCTL0_ST B0ST_1
143#endif
144
145#if (flash_EBIU_AMBCTL_HT > 2)
146#define flash_EBIU_AMBCTL0_HT B0HT_3
147#endif
148#if (flash_EBIU_AMBCTL_HT == 2)
149#define flash_EBIU_AMBCTL0_HT B0HT_2
150#endif
151#if (flash_EBIU_AMBCTL_HT == 1)
152#define flash_EBIU_AMBCTL0_HT B0HT_1
153#endif
154#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
155#define flash_EBIU_AMBCTL0_HT B0HT_0
156#endif
157#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
158#define flash_EBIU_AMBCTL0_HT B0HT_1
159#endif
160
161#if (flash_EBIU_AMBCTL_WAT > 14)
162#define flash_EBIU_AMBCTL0_WAT B0WAT_15
163#endif
164#if (flash_EBIU_AMBCTL_WAT == 14)
165#define flash_EBIU_AMBCTL0_WAT B0WAT_14
166#endif
167#if (flash_EBIU_AMBCTL_WAT == 13)
168#define flash_EBIU_AMBCTL0_WAT B0WAT_13
169#endif
170#if (flash_EBIU_AMBCTL_WAT == 12)
171#define flash_EBIU_AMBCTL0_WAT B0WAT_12
172#endif
173#if (flash_EBIU_AMBCTL_WAT == 11)
174#define flash_EBIU_AMBCTL0_WAT B0WAT_11
175#endif
176#if (flash_EBIU_AMBCTL_WAT == 10)
177#define flash_EBIU_AMBCTL0_WAT B0WAT_10
178#endif
179#if (flash_EBIU_AMBCTL_WAT == 9)
180#define flash_EBIU_AMBCTL0_WAT B0WAT_9
181#endif
182#if (flash_EBIU_AMBCTL_WAT == 8)
183#define flash_EBIU_AMBCTL0_WAT B0WAT_8
184#endif
185#if (flash_EBIU_AMBCTL_WAT == 7)
186#define flash_EBIU_AMBCTL0_WAT B0WAT_7
187#endif
188#if (flash_EBIU_AMBCTL_WAT == 6)
189#define flash_EBIU_AMBCTL0_WAT B0WAT_6
190#endif
191#if (flash_EBIU_AMBCTL_WAT == 5)
192#define flash_EBIU_AMBCTL0_WAT B0WAT_5
193#endif
194#if (flash_EBIU_AMBCTL_WAT == 4)
195#define flash_EBIU_AMBCTL0_WAT B0WAT_4
196#endif
197#if (flash_EBIU_AMBCTL_WAT == 3)
198#define flash_EBIU_AMBCTL0_WAT B0WAT_3
199#endif
200#if (flash_EBIU_AMBCTL_WAT == 2)
201#define flash_EBIU_AMBCTL0_WAT B0WAT_2
202#endif
203#if (flash_EBIU_AMBCTL_WAT == 1)
204#define flash_EBIU_AMBCTL0_WAT B0WAT_1
205#endif
206
207#if (flash_EBIU_AMBCTL_RAT > 14)
208#define flash_EBIU_AMBCTL0_RAT B0RAT_15
209#endif
210#if (flash_EBIU_AMBCTL_RAT == 14)
211#define flash_EBIU_AMBCTL0_RAT B0RAT_14
212#endif
213#if (flash_EBIU_AMBCTL_RAT == 13)
214#define flash_EBIU_AMBCTL0_RAT B0RAT_13
215#endif
216#if (flash_EBIU_AMBCTL_RAT == 12)
217#define flash_EBIU_AMBCTL0_RAT B0RAT_12
218#endif
219#if (flash_EBIU_AMBCTL_RAT == 11)
220#define flash_EBIU_AMBCTL0_RAT B0RAT_11
221#endif
222#if (flash_EBIU_AMBCTL_RAT == 10)
223#define flash_EBIU_AMBCTL0_RAT B0RAT_10
224#endif
225#if (flash_EBIU_AMBCTL_RAT == 9)
226#define flash_EBIU_AMBCTL0_RAT B0RAT_9
227#endif
228#if (flash_EBIU_AMBCTL_RAT == 8)
229#define flash_EBIU_AMBCTL0_RAT B0RAT_8
230#endif
231#if (flash_EBIU_AMBCTL_RAT == 7)
232#define flash_EBIU_AMBCTL0_RAT B0RAT_7
233#endif
234#if (flash_EBIU_AMBCTL_RAT == 6)
235#define flash_EBIU_AMBCTL0_RAT B0RAT_6
236#endif
237#if (flash_EBIU_AMBCTL_RAT == 5)
238#define flash_EBIU_AMBCTL0_RAT B0RAT_5
239#endif
240#if (flash_EBIU_AMBCTL_RAT == 4)
241#define flash_EBIU_AMBCTL0_RAT B0RAT_4
242#endif
243#if (flash_EBIU_AMBCTL_RAT == 3)
244#define flash_EBIU_AMBCTL0_RAT B0RAT_3
245#endif
246#if (flash_EBIU_AMBCTL_RAT == 2)
247#define flash_EBIU_AMBCTL0_RAT B0RAT_2
248#endif
249#if (flash_EBIU_AMBCTL_RAT == 1)
250#define flash_EBIU_AMBCTL0_RAT B0RAT_1
251#endif
252
253#define flash_EBIU_AMBCTL0 \
254 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
255 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
index a2228428dc06..70b9c1194024 100644
--- a/arch/blackfin/mach-bf548/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h
@@ -108,4 +108,10 @@
108#define L1_SCRATCH_START 0xFFB00000 108#define L1_SCRATCH_START 0xFFB00000
109#define L1_SCRATCH_LENGTH 0x1000 109#define L1_SCRATCH_LENGTH 0x1000
110 110
111#define GET_PDA_SAFE(preg) \
112 preg.l = _cpu_pda; \
113 preg.h = _cpu_pda;
114
115#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
116
111#endif/* _MEM_MAP_548_H_ */ 117#endif/* _MEM_MAP_548_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 21:14:52 -0500