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-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h66
2 files changed, 0 insertions, 72 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 13302b67857a..5684030ccc21 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -64,10 +64,4 @@
64#define OFFSET_THR 0x28 /* Transmit Holding register */ 64#define OFFSET_THR 0x28 /* Transmit Holding register */
65#define OFFSET_RBR 0x2C /* Receive Buffer register */ 65#define OFFSET_RBR 0x2C /* Receive Buffer register */
66 66
67/* PLL_DIV Masks */
68#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
69#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
70#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
71#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
72
73#endif 67#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 855bc608c8e7..6d97b4e892b4 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2075,26 +2075,6 @@
2075#define AFEXIT 0x10 /* Authentication Firmware Exit */ 2075#define AFEXIT 0x10 /* Authentication Firmware Exit */
2076#define SECSTAT 0xe0 /* Secure Status */ 2076#define SECSTAT 0xe0 /* Secure Status */
2077 2077
2078/* Bit masks for PLL_DIV */
2079
2080#define CSEL 0x30 /* Core Select */
2081#define SSEL 0xf /* System Select */
2082#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2083#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2084#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2085#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2086
2087/* Bit masks for PLL_CTL */
2088
2089#define MSEL 0x7e00 /* Multiplier Select */
2090#define BYPASS 0x100 /* PLL Bypass Enable */
2091#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
2092#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
2093#define PDWN 0x20 /* Power Down */
2094#define STOPCK 0x8 /* Stop Clock */
2095#define PLL_OFF 0x2 /* Disable PLL */
2096#define DF 0x1 /* Divide Frequency */
2097
2098/* SWRST Masks */ 2078/* SWRST Masks */
2099#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 2079#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
2100#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 2080#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
@@ -2102,52 +2082,6 @@
2102#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 2082#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
2103#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 2083#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
2104 2084
2105/* Bit masks for PLL_STAT */
2106
2107#define PLL_LOCKED 0x20 /* PLL Locked Status */
2108#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2109#define FULL_ON 0x2 /* Full-On Mode */
2110#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
2111#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
2112#define CANWS 0x800 /* CAN Wake-Up Status */
2113#define USBWS 0x2000 /* USB Wake-Up Status */
2114#define KPADWS 0x4000 /* Keypad Wake-Up Status */
2115#define ROTWS 0x8000 /* Rotary Wake-Up Status */
2116#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
2117
2118/* Bit masks for VR_CTL */
2119
2120#define FREQ 0x3 /* Regulator Switching Frequency */
2121#define GAIN 0xc /* Voltage Output Level Gain */
2122#define VLEV 0xf0 /* Internal Voltage Level */
2123#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
2124#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
2125#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
2126#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
2127#define USBWE 0x800 /* USB Wake-Up Enable */
2128#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2129#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2130
2131#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
2132#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
2133#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
2134
2135#define GAIN_5 0x0000 /* GAIN = 5*/
2136#define GAIN_10 0x0004 /* GAIN = 1*/
2137#define GAIN_20 0x0008 /* GAIN = 2*/
2138#define GAIN_50 0x000C /* GAIN = 5*/
2139
2140#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
2141#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
2142#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
2143#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
2144#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
2145#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
2146#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
2147#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
2148#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
2149#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
2150
2151/* Bit masks for NFC_CTL */ 2085/* Bit masks for NFC_CTL */
2152 2086
2153#define WR_DLY 0xf /* Write Strobe Delay */ 2087#define WR_DLY 0xf /* Write Strobe Delay */