diff options
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/dma.h')
-rw-r--r-- | arch/blackfin/mach-bf548/include/mach/dma.h | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h index a30d242c7398..1a1091b071fd 100644 --- a/arch/blackfin/mach-bf548/include/mach/dma.h +++ b/arch/blackfin/mach-bf548/include/mach/dma.h | |||
@@ -27,17 +27,37 @@ | |||
27 | #define CH_PIXC_OVERLAY 16 | 27 | #define CH_PIXC_OVERLAY 16 |
28 | #define CH_PIXC_OUTPUT 17 | 28 | #define CH_PIXC_OUTPUT 17 |
29 | #define CH_SPORT2_RX 18 | 29 | #define CH_SPORT2_RX 18 |
30 | #define CH_UART2_RX 18 | ||
31 | #define CH_SPORT2_TX 19 | 30 | #define CH_SPORT2_TX 19 |
32 | #define CH_UART2_TX 19 | ||
33 | #define CH_SPORT3_RX 20 | 31 | #define CH_SPORT3_RX 20 |
34 | #define CH_UART3_RX 20 | ||
35 | #define CH_SPORT3_TX 21 | 32 | #define CH_SPORT3_TX 21 |
36 | #define CH_UART3_TX 21 | ||
37 | #define CH_SDH 22 | 33 | #define CH_SDH 22 |
38 | #define CH_NFC 22 | 34 | #define CH_NFC 22 |
39 | #define CH_SPI2 23 | 35 | #define CH_SPI2 23 |
40 | 36 | ||
37 | #if defined(CONFIG_UART2_DMA_RX_ON_DMA13) | ||
38 | #define CH_UART2_RX 13 | ||
39 | #define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */ | ||
40 | #define CH_UART2_TX 14 | ||
41 | #define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */ | ||
42 | #else /* Default USE SPORT2's DMA Channel */ | ||
43 | #define CH_UART2_RX 18 | ||
44 | #define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ | ||
45 | #define CH_UART2_TX 19 | ||
46 | #define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ | ||
47 | #endif | ||
48 | |||
49 | #if defined(CONFIG_UART3_DMA_RX_ON_DMA15) | ||
50 | #define CH_UART3_RX 15 | ||
51 | #define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */ | ||
52 | #define CH_UART3_TX 16 | ||
53 | #define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */ | ||
54 | #else /* Default USE SPORT3's DMA Channel */ | ||
55 | #define CH_UART3_RX 20 | ||
56 | #define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ | ||
57 | #define CH_UART3_TX 21 | ||
58 | #define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ | ||
59 | #endif | ||
60 | |||
41 | #define CH_MEM_STREAM0_DEST 24 | 61 | #define CH_MEM_STREAM0_DEST 24 |
42 | #define CH_MEM_STREAM0_SRC 25 | 62 | #define CH_MEM_STREAM0_SRC 25 |
43 | #define CH_MEM_STREAM1_DEST 26 | 63 | #define CH_MEM_STREAM1_DEST 26 |