1 files changed, 3 insertions, 133 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 72c343646b2a..be21ba5b3aa8 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -99,15 +99,15 @@
 #define                     TWI1_REGBASE  0xffc02200
 #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
 #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
+#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
 #define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
 #define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
+#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
 #define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
 #define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
 #define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
 #define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
+#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
 #define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
 #define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
 #define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
@@ -646,136 +646,6 @@
 #define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-/* Bit masks for SDH_COMMAND */
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-/* Bit masks for SDH_PWR_CTL */
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-/* Bit masks for SDH_CLK_CTL */
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-/* Bit masks for SDH_RESP_CMD */
-#define                  RESP_CMD  0x3f       /* Response Command */
-/* Bit masks for SDH_DATA_CTL */
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-/* Bit masks for SDH_STATUS */
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-/* Bit masks for SDH_STATUS_CLR */
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-/* Bit masks for SDH_MASK0 */
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-/* Bit masks for SDH_FIFO_CNT */
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-/* Bit masks for SDH_E_STATUS */
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-/* Bit masks for SDH_E_MASK */
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-/* Bit masks for SDH_CFG */
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-/* Bit masks for SDH_RD_WAIT_EN */
-#define                       RWR  0x1        /* Read Wait Request */
 /* Bit masks for ATAPI_CONTROL */
 #define                 PIO_START  0x1        /* Start PIO/Reg Op */

diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index 72c343646b2a..be21ba5b3aa8 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -99,15 +99,15 @@
99	#define TWI1_REGBASE 0xffc02200	99	#define TWI1_REGBASE 0xffc02200
100	#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */	100	#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
101	#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */	101	#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
102	#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */	102	#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
103	#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */	103	#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
104	#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */	104	#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
105	#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */	105	#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
106	#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */	106	#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
107	#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */	107	#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
108	#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */	108	#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
109	#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */	109	#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
110	#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */	110	#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
111	#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */	111	#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
112	#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */	112	#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
113	#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */	113	#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
@@ -646,136 +646,6 @@
646		646
647	#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */	647	#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
648		648
649	/* Bit masks for SDH_COMMAND */
650
651	#define CMD_IDX 0x3f /* Command Index */
652	#define CMD_RSP 0x40 /* Response */
653	#define CMD_L_RSP 0x80 /* Long Response */
654	#define CMD_INT_E 0x100 /* Command Interrupt */
655	#define CMD_PEND_E 0x200 /* Command Pending */
656	#define CMD_E 0x400 /* Command Enable */
657
658	/* Bit masks for SDH_PWR_CTL */
659
660	#define PWR_ON 0x3 /* Power On */
661	#if 0
662	#define TBD 0x3c /* TBD */
663	#endif
664	#define SD_CMD_OD 0x40 /* Open Drain Output */
665	#define ROD_CTL 0x80 /* Rod Control */
666
667	/* Bit masks for SDH_CLK_CTL */
668
669	#define CLKDIV 0xff /* MC_CLK Divisor */
670	#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
671	#define PWR_SV_E 0x200 /* Power Save Enable */
672	#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
673	#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
674
675	/* Bit masks for SDH_RESP_CMD */
676
677	#define RESP_CMD 0x3f /* Response Command */
678
679	/* Bit masks for SDH_DATA_CTL */
680
681	#define DTX_E 0x1 /* Data Transfer Enable */
682	#define DTX_DIR 0x2 /* Data Transfer Direction */
683	#define DTX_MODE 0x4 /* Data Transfer Mode */
684	#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
685	#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
686
687	/* Bit masks for SDH_STATUS */
688
689	#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
690	#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
691	#define CMD_TIME_OUT 0x4 /* CMD Time Out */
692	#define DAT_TIME_OUT 0x8 /* Data Time Out */
693	#define TX_UNDERRUN 0x10 /* Transmit Underrun */
694	#define RX_OVERRUN 0x20 /* Receive Overrun */
695	#define CMD_RESP_END 0x40 /* CMD Response End */
696	#define CMD_SENT 0x80 /* CMD Sent */
697	#define DAT_END 0x100 /* Data End */
698	#define START_BIT_ERR 0x200 /* Start Bit Error */
699	#define DAT_BLK_END 0x400 /* Data Block End */
700	#define CMD_ACT 0x800 /* CMD Active */
701	#define TX_ACT 0x1000 /* Transmit Active */
702	#define RX_ACT 0x2000 /* Receive Active */
703	#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
704	#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
705	#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
706	#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
707	#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
708	#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
709	#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
710	#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
711
712	/* Bit masks for SDH_STATUS_CLR */
713
714	#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
715	#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
716	#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
717	#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
718	#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
719	#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
720	#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
721	#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
722	#define DAT_END_STAT 0x100 /* Data End Status */
723	#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
724	#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
725
726	/* Bit masks for SDH_MASK0 */
727
728	#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
729	#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
730	#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
731	#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
732	#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
733	#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
734	#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
735	#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
736	#define DAT_END_MASK 0x100 /* Data End Mask */
737	#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
738	#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
739	#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
740	#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
741	#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
742	#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
743	#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
744	#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
745	#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
746	#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
747	#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
748	#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
749	#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
750
751	/* Bit masks for SDH_FIFO_CNT */
752
753	#define FIFO_COUNT 0x7fff /* FIFO Count */
754
755	/* Bit masks for SDH_E_STATUS */
756
757	#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
758	#define SD_CARD_DET 0x10 /* SD Card Detect */
759
760	/* Bit masks for SDH_E_MASK */
761
762	#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
763	#define SCD_MSK 0x40 /* Mask Card Detect */
764
765	/* Bit masks for SDH_CFG */
766
767	#define CLKS_EN 0x1 /* Clocks Enable */
768	#define SD4E 0x4 /* SDIO 4-Bit Enable */
769	#define MWE 0x8 /* Moving Window Enable */
770	#define SD_RST 0x10 /* SDMMC Reset */
771	#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
772	#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
773	#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
774
775	/* Bit masks for SDH_RD_WAIT_EN */
776
777	#define RWR 0x1 /* Read Wait Request */
778
779	/* Bit masks for ATAPI_CONTROL */	649	/* Bit masks for ATAPI_CONTROL */
780		650
781	#define PIO_START 0x1 /* Start PIO/Reg Op */	651	#define PIO_START 0x1 /* Start PIO/Reg Op */