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diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
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1/*
2 * File: include/asm-blackfin/mach-bf548/bf548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: System MMR register and memory map for ADSP-BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF548_H__
31#define __MACH_BF548_H__
32
33#define SUPPORTED_REVID 0
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54
55#define BFIN_DSUBBANKS 4
56#define BFIN_DWAYS 2
57#define BFIN_DLINES 64
58#define BFIN_ISUBBANKS 4
59#define BFIN_IWAYS 4
60#define BFIN_ILINES 32
61
62#define WAY0_L 0x1
63#define WAY1_L 0x2
64#define WAY01_L 0x3
65#define WAY2_L 0x4
66#define WAY02_L 0x5
67#define WAY12_L 0x6
68#define WAY012_L 0x7
69
70#define WAY3_L 0x8
71#define WAY03_L 0x9
72#define WAY13_L 0xA
73#define WAY013_L 0xB
74
75#define WAY32_L 0xC
76#define WAY320_L 0xD
77#define WAY321_L 0xE
78#define WAYALL_L 0xF
79
80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
81
82/********************************* EBIU Settings ************************************/
83#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
84#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
85
86#ifdef CONFIG_C_AMBEN_ALL
87#define V_AMBEN AMBEN_ALL
88#endif
89#ifdef CONFIG_C_AMBEN
90#define V_AMBEN 0x0
91#endif
92#ifdef CONFIG_C_AMBEN_B0
93#define V_AMBEN AMBEN_B0
94#endif
95#ifdef CONFIG_C_AMBEN_B0_B1
96#define V_AMBEN AMBEN_B0_B1
97#endif
98#ifdef CONFIG_C_AMBEN_B0_B1_B2
99#define V_AMBEN AMBEN_B0_B1_B2
100#endif
101#ifdef CONFIG_C_AMCKEN
102#define V_AMCKEN AMCKEN
103#else
104#define V_AMCKEN 0x0
105#endif
106
107#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
108
109#if defined(CONFIG_BF542)
110# define CPU "BF542"
111# define CPUID 0x027c8000
112#elif defined(CONFIG_BF544)
113# define CPU "BF544"
114# define CPUID 0x027c8000
115#elif defined(CONFIG_BF547)
116# define CPU "BF547"
117#elif defined(CONFIG_BF548)
118# define CPU "BF548"
119# define CPUID 0x027c6000
120#elif defined(CONFIG_BF549)
121# define CPU "BF549"
122#else
123# define CPU "UNKNOWN"
124# define CPUID 0x0
125#endif
126
127#endif /* __MACH_BF48_H__ */