diff options
Diffstat (limited to 'arch/blackfin/mach-bf548/head.S')
-rw-r--r-- | arch/blackfin/mach-bf548/head.S | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index 745662e88759..74fe258421a5 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S | |||
@@ -324,12 +324,25 @@ ENTRY(_start_dma_code) | |||
324 | w[p0] = r0.l; | 324 | w[p0] = r0.l; |
325 | ssync; | 325 | ssync; |
326 | 326 | ||
327 | #if defined(CONFIG_BF54x) | ||
328 | P2.H = hi(EBIU_RSTCTL); | ||
329 | P2.L = lo(EBIU_RSTCTL); | ||
330 | R0 = [P2]; | ||
331 | BITSET (R0, 3); | ||
332 | #else | ||
327 | P2.H = hi(EBIU_SDGCTL); | 333 | P2.H = hi(EBIU_SDGCTL); |
328 | P2.L = lo(EBIU_SDGCTL); | 334 | P2.L = lo(EBIU_SDGCTL); |
329 | R0 = [P2]; | 335 | R0 = [P2]; |
330 | BITSET (R0, 24); | 336 | BITSET (R0, 24); |
337 | #endif | ||
331 | [P2] = R0; | 338 | [P2] = R0; |
332 | SSYNC; | 339 | SSYNC; |
340 | #if defined(CONFIG_BF54x) | ||
341 | .LSRR_MODE: | ||
342 | R0 = [P2]; | ||
343 | CC = BITTST(R0, 4); | ||
344 | if !CC JUMP .LSRR_MODE; | ||
345 | #endif | ||
333 | 346 | ||
334 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ | 347 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ |
335 | r0 = r0 << 9; /* Shift it over, */ | 348 | r0 = r0 << 9; /* Shift it over, */ |
@@ -361,6 +374,39 @@ ENTRY(_start_dma_code) | |||
361 | w[p0] = r0.l; | 374 | w[p0] = r0.l; |
362 | ssync; | 375 | ssync; |
363 | 376 | ||
377 | #if defined(CONFIG_BF54x) | ||
378 | P2.H = hi(EBIU_RSTCTL); | ||
379 | P2.L = lo(EBIU_RSTCTL); | ||
380 | R0 = [P2]; | ||
381 | CC = BITTST(R0, 0); | ||
382 | if CC jump .Lskipddrrst; | ||
383 | BITSET (R0, 0); | ||
384 | .Lskipddrrst: | ||
385 | BITCLR (R0, 3); | ||
386 | [P2] = R0; | ||
387 | SSYNC; | ||
388 | |||
389 | p0.l = lo(EBIU_DDRCTL0); | ||
390 | p0.h = hi(EBIU_DDRCTL0); | ||
391 | r0.l = lo(mem_DDRCTL0); | ||
392 | r0.h = hi(mem_DDRCTL0); | ||
393 | [p0] = r0; | ||
394 | ssync; | ||
395 | |||
396 | p0.l = lo(EBIU_DDRCTL1); | ||
397 | p0.h = hi(EBIU_DDRCTL1); | ||
398 | r0.l = lo(mem_DDRCTL1); | ||
399 | r0.h = hi(mem_DDRCTL1); | ||
400 | [p0] = r0; | ||
401 | ssync; | ||
402 | |||
403 | p0.l = lo(EBIU_DDRCTL2); | ||
404 | p0.h = hi(EBIU_DDRCTL2); | ||
405 | r0.l = lo(mem_DDRCTL2); | ||
406 | r0.h = hi(mem_DDRCTL2); | ||
407 | [p0] = r0; | ||
408 | ssync; | ||
409 | #else | ||
364 | p0.l = lo(EBIU_SDRRC); | 410 | p0.l = lo(EBIU_SDRRC); |
365 | p0.h = hi(EBIU_SDRRC); | 411 | p0.h = hi(EBIU_SDRRC); |
366 | r0 = mem_SDRRC; | 412 | r0 = mem_SDRRC; |
@@ -394,6 +440,7 @@ ENTRY(_start_dma_code) | |||
394 | R1 = R1 | R0; | 440 | R1 = R1 | R0; |
395 | [P2] = R1; | 441 | [P2] = R1; |
396 | SSYNC; | 442 | SSYNC; |
443 | #endif | ||
397 | 444 | ||
398 | p0.h = hi(SIC_IWR0); | 445 | p0.h = hi(SIC_IWR0); |
399 | p0.l = lo(SIC_IWR0); | 446 | p0.l = lo(SIC_IWR0); |