aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-bf548/head.S
diff options
context:
space:
mode:
Diffstat (limited to 'arch/blackfin/mach-bf548/head.S')
-rw-r--r--arch/blackfin/mach-bf548/head.S52
1 files changed, 7 insertions, 45 deletions
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 4d5cfeacb123..051b05c88027 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -73,25 +73,19 @@ ENTRY(_start_dma_code)
73 w[p0] = r0.l; 73 w[p0] = r0.l;
74 ssync; 74 ssync;
75 75
76#if defined(CONFIG_BF54x) 76 /* enable self refresh via SRREQ */
77 P2.H = hi(EBIU_RSTCTL); 77 P2.H = hi(EBIU_RSTCTL);
78 P2.L = lo(EBIU_RSTCTL); 78 P2.L = lo(EBIU_RSTCTL);
79 R0 = [P2]; 79 R0 = [P2];
80 BITSET (R0, 3); 80 BITSET (R0, 3);
81#else
82 P2.H = hi(EBIU_SDGCTL);
83 P2.L = lo(EBIU_SDGCTL);
84 R0 = [P2];
85 BITSET (R0, 24);
86#endif
87 [P2] = R0; 81 [P2] = R0;
88 SSYNC; 82 SSYNC;
89#if defined(CONFIG_BF54x) 83
84 /* wait for SRACK bit to be set */
90.LSRR_MODE: 85.LSRR_MODE:
91 R0 = [P2]; 86 R0 = [P2];
92 CC = BITTST(R0, 4); 87 CC = BITTST(R0, 4);
93 if !CC JUMP .LSRR_MODE; 88 if !CC JUMP .LSRR_MODE;
94#endif
95 89
96 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ 90 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
97 r0 = r0 << 9; /* Shift it over, */ 91 r0 = r0 << 9; /* Shift it over, */
@@ -100,6 +94,9 @@ ENTRY(_start_dma_code)
100 r1 = PLL_BYPASS; /* Bypass the PLL? */ 94 r1 = PLL_BYPASS; /* Bypass the PLL? */
101 r1 = r1 << 8; /* Shift it over */ 95 r1 = r1 << 8; /* Shift it over */
102 r0 = r1 | r0; /* add them all together */ 96 r0 = r1 | r0; /* add them all together */
97#ifdef ANOMALY_05000265
98 r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
99#endif
103 100
104 p0.h = hi(PLL_CTL); 101 p0.h = hi(PLL_CTL);
105 p0.l = lo(PLL_CTL); /* Load the address */ 102 p0.l = lo(PLL_CTL); /* Load the address */
@@ -123,7 +120,7 @@ ENTRY(_start_dma_code)
123 w[p0] = r0.l; 120 w[p0] = r0.l;
124 ssync; 121 ssync;
125 122
126#if defined(CONFIG_BF54x) 123 /* disable self refresh by clearing SRREQ */
127 P2.H = hi(EBIU_RSTCTL); 124 P2.H = hi(EBIU_RSTCTL);
128 P2.L = lo(EBIU_RSTCTL); 125 P2.L = lo(EBIU_RSTCTL);
129 R0 = [P2]; 126 R0 = [P2];
@@ -155,41 +152,6 @@ ENTRY(_start_dma_code)
155 r0.h = hi(mem_DDRCTL2); 152 r0.h = hi(mem_DDRCTL2);
156 [p0] = r0; 153 [p0] = r0;
157 ssync; 154 ssync;
158#else
159 p0.l = lo(EBIU_SDRRC);
160 p0.h = hi(EBIU_SDRRC);
161 r0 = mem_SDRRC;
162 w[p0] = r0.l;
163 ssync;
164
165 p0.l = LO(EBIU_SDBCTL);
166 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
167 r0 = mem_SDBCTL;
168 w[p0] = r0.l;
169 ssync;
170
171 P2.H = hi(EBIU_SDGCTL);
172 P2.L = lo(EBIU_SDGCTL);
173 R0 = [P2];
174 BITCLR (R0, 24);
175 p0.h = hi(EBIU_SDSTAT);
176 p0.l = lo(EBIU_SDSTAT);
177 r2.l = w[p0];
178 cc = bittst(r2,3);
179 if !cc jump .Lskip;
180 NOP;
181 BITSET (R0, 23);
182.Lskip:
183 [P2] = R0;
184 SSYNC;
185
186 R0.L = lo(mem_SDGCTL);
187 R0.H = hi(mem_SDGCTL);
188 R1 = [p2];
189 R1 = R1 | R0;
190 [P2] = R1;
191 SSYNC;
192#endif
193 155
194 RTS; 156 RTS;
195ENDPROC(_start_dma_code) 157ENDPROC(_start_dma_code)