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-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h75
2 files changed, 0 insertions, 81 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 278e8942eef2..08b5eabb1ed5 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -37,10 +37,4 @@
37#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 37#define OFFSET_SCR 0x1C /* SCR Scratch Register */
38#define OFFSET_GCTL 0x24 /* Global Control Register */ 38#define OFFSET_GCTL 0x24 /* Global Control Register */
39 39
40/* PLL_DIV Masks */
41#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
42#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
43#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
44#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
45
46#endif 40#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 312686a5194d..5375819b6147 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1422,81 +1422,6 @@
1422/* System MMR Register Bits and Macros */ 1422/* System MMR Register Bits and Macros */
1423/******************************************************************************* */ 1423/******************************************************************************* */
1424 1424
1425/* ********************* PLL AND RESET MASKS ************************ */
1426/* PLL_CTL Masks */
1427#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
1428#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
1429#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
1430#define PLL_OFF 0x0002 /* Shut off PLL clocks */
1431
1432#define STOPCK 0x0008 /* Core Clock Off */
1433#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
1434#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
1435#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
1436#define BYPASS 0x0100 /* Bypass the PLL */
1437#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
1438
1439/* PLL_CTL Macros */
1440#ifdef _MISRA_RULES
1441#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1442#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6)
1443#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
1444#else
1445#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1446#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
1447#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
1448#endif /* _MISRA_RULES */
1449
1450/* PLL_DIV Masks */
1451#define SSEL 0x000F /* System Select */
1452#define CSEL 0x0030 /* Core Select */
1453#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
1454#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
1455#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
1456#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1457
1458#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
1459
1460/* PLL_DIV Macros */
1461#ifdef _MISRA_RULES
1462#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1463#else
1464#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1465#endif /* _MISRA_RULES */
1466
1467/* PLL_STAT Masks */
1468#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1469#define FULL_ON 0x0002 /* Processor In Full On Mode */
1470#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1471#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1472
1473/* VR_CTL Masks */
1474#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1475#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1476#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1477#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1478#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1479
1480#define GAIN 0x000C /* Voltage Level Gain */
1481#define GAIN_5 0x0000 /* GAIN = 5 */
1482#define GAIN_10 0x0004 /* GAIN = 10 */
1483#define GAIN_20 0x0008 /* GAIN = 20 */
1484#define GAIN_50 0x000C /* GAIN = 50 */
1485
1486#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
1487#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
1488#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
1489#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
1490#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
1491#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
1492#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
1493#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
1494
1495#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1496#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1497#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
1498#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
1499
1500/* SWRST Mask */ 1425/* SWRST Mask */
1501#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 1426#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1502#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 1427#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */