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-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h10
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 9496196ac164..5ecee1690957 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -47,11 +47,6 @@
47#endif 47#endif
48#endif 48#endif
49 49
50/* UART_IIR Register */
51#define STATUS(x) ((x << 1) & 0x06)
52#define STATUS_P1 0x02
53#define STATUS_P0 0x01
54
55#define BFIN_UART_NR_PORTS 3 50#define BFIN_UART_NR_PORTS 3
56 51
57#define OFFSET_THR 0x00 /* Transmit Holding register */ 52#define OFFSET_THR 0x00 /* Transmit Holding register */
@@ -67,11 +62,6 @@
67#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 62#define OFFSET_SCR 0x1C /* SCR Scratch Register */
68#define OFFSET_GCTL 0x24 /* Global Control Register */ 63#define OFFSET_GCTL 0x24 /* Global Control Register */
69 64
70/* DPMC*/
71#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
72#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
73#define STOPCK_OFF STOPCK
74
75/* PLL_DIV Masks */ 65/* PLL_DIV Masks */
76#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 66#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
77#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ 67#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */