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-rw-r--r--arch/blackfin/mach-bf538/Makefile1
-rw-r--r--arch/blackfin/mach-bf538/ext-gpio.c123
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h42
-rw-r--r--arch/blackfin/mach-bf538/include/mach/gpio.h7
-rw-r--r--arch/blackfin/mach-bf538/include/mach/portmux.h2
5 files changed, 148 insertions, 27 deletions
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile
index 8cd2719684db..c0be54f2cd2b 100644
--- a/arch/blackfin/mach-bf538/Makefile
+++ b/arch/blackfin/mach-bf538/Makefile
@@ -3,3 +3,4 @@
3# 3#
4 4
5obj-y := ints-priority.o dma.o 5obj-y := ints-priority.o dma.o
6obj-$(CONFIG_GPIOLIB) += ext-gpio.o
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
new file mode 100644
index 000000000000..180b1252679f
--- /dev/null
+++ b/arch/blackfin/mach-bf538/ext-gpio.c
@@ -0,0 +1,123 @@
1/*
2 * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
3 *
4 * Copyright 2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/err.h>
11#include <asm/blackfin.h>
12#include <asm/gpio.h>
13#include <asm/portmux.h>
14
15#define DEFINE_REG(reg, off) \
16static inline u16 read_##reg(void __iomem *port) \
17 { return bfin_read16(port + off); } \
18static inline void write_##reg(void __iomem *port, u16 v) \
19 { bfin_write16(port + off, v); }
20
21DEFINE_REG(PORTIO, 0x00)
22DEFINE_REG(PORTIO_CLEAR, 0x10)
23DEFINE_REG(PORTIO_SET, 0x20)
24DEFINE_REG(PORTIO_DIR, 0x40)
25DEFINE_REG(PORTIO_INEN, 0x50)
26
27static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
28{
29 switch (chip->base) {
30 default: /* not really needed, but keeps gcc happy */
31 case GPIO_PC0: return (void __iomem *)PORTCIO;
32 case GPIO_PD0: return (void __iomem *)PORTDIO;
33 case GPIO_PE0: return (void __iomem *)PORTEIO;
34 }
35}
36
37static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
38{
39 void __iomem *port = gpio_chip_to_mmr(chip);
40 return !!(read_PORTIO(port) & (1u << gpio));
41}
42
43static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
44{
45 void __iomem *port = gpio_chip_to_mmr(chip);
46 if (value)
47 write_PORTIO_SET(port, (1u << gpio));
48 else
49 write_PORTIO_CLEAR(port, (1u << gpio));
50}
51
52static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
53{
54 void __iomem *port = gpio_chip_to_mmr(chip);
55 write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
56 write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
57 return 0;
58}
59
60static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
61{
62 void __iomem *port = gpio_chip_to_mmr(chip);
63 write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
64 bf538_gpio_set_value(port, gpio, value);
65 write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
66 return 0;
67}
68
69static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
70{
71 return bfin_special_gpio_request(chip->base + gpio, chip->label);
72}
73
74static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
75{
76 return bfin_special_gpio_free(chip->base + gpio);
77}
78
79/* We don't set the irq fields as these banks cannot generate interrupts */
80
81static struct gpio_chip bf538_portc_chip = {
82 .label = "GPIO-PC",
83 .direction_input = bf538_gpio_direction_input,
84 .get = bf538_gpio_get_value,
85 .direction_output = bf538_gpio_direction_output,
86 .set = bf538_gpio_set_value,
87 .request = bf538_gpio_request,
88 .free = bf538_gpio_free,
89 .base = GPIO_PC0,
90 .ngpio = GPIO_PC9 - GPIO_PC0 + 1,
91};
92
93static struct gpio_chip bf538_portd_chip = {
94 .label = "GPIO-PD",
95 .direction_input = bf538_gpio_direction_input,
96 .get = bf538_gpio_get_value,
97 .direction_output = bf538_gpio_direction_output,
98 .set = bf538_gpio_set_value,
99 .request = bf538_gpio_request,
100 .free = bf538_gpio_free,
101 .base = GPIO_PD0,
102 .ngpio = GPIO_PD13 - GPIO_PD0 + 1,
103};
104
105static struct gpio_chip bf538_porte_chip = {
106 .label = "GPIO-PE",
107 .direction_input = bf538_gpio_direction_input,
108 .get = bf538_gpio_get_value,
109 .direction_output = bf538_gpio_direction_output,
110 .set = bf538_gpio_set_value,
111 .request = bf538_gpio_request,
112 .free = bf538_gpio_free,
113 .base = GPIO_PE0,
114 .ngpio = GPIO_PE15 - GPIO_PE0 + 1,
115};
116
117static int __init bf538_extgpio_setup(void)
118{
119 return gpiochip_add(&bf538_portc_chip) |
120 gpiochip_add(&bf538_portd_chip) |
121 gpiochip_add(&bf538_porte_chip);
122}
123arch_initcall(bf538_extgpio_setup);
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 5f6c34dfd08e..1f1aeabc8c89 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -468,31 +468,31 @@
468/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ 468/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
469 469
470/* GPIO Port C Register Names */ 470/* GPIO Port C Register Names */
471#define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */ 471#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
472#define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */ 472#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
473#define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */ 473#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
474#define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */ 474#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
475#define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */ 475#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
476#define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ 476#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
477#define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ 477#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
478 478
479/* GPIO Port D Register Names */ 479/* GPIO Port D Register Names */
480#define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */ 480#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
481#define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */ 481#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
482#define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */ 482#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
483#define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */ 483#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
484#define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */ 484#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
485#define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ 485#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
486#define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ 486#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
487 487
488/* GPIO Port E Register Names */ 488/* GPIO Port E Register Names */
489#define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */ 489#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
490#define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */ 490#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
491#define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */ 491#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
492#define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */ 492#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
493#define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */ 493#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
494#define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ 494#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
495#define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ 495#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
496 496
497/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ 497/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
498 498
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index 295c78a465c2..0c346fba9619 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2008 Analog Devices Inc. 2 * Copyright (C) 2008-2009 Analog Devices Inc.
3 * Licensed under the GPL-2 or later. 3 * Licensed under the GPL-2 or later.
4 */ 4 */
5 5
@@ -7,11 +7,8 @@
7#ifndef _MACH_GPIO_H_ 7#ifndef _MACH_GPIO_H_
8#define _MACH_GPIO_H_ 8#define _MACH_GPIO_H_
9 9
10 /* FIXME:
11 * For now only support PORTF GPIOs.
12 * PORT C,D and E are for peripheral usage only
13 */
14#define MAX_BLACKFIN_GPIOS 16 10#define MAX_BLACKFIN_GPIOS 16
11#define BFIN_SPECIAL_GPIO_BANKS 3
15 12
16#define GPIO_PF0 0 /* PF */ 13#define GPIO_PF0 0 /* PF */
17#define GPIO_PF1 1 14#define GPIO_PF1 1
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
index 6121cf8b5872..0083ba13ee9e 100644
--- a/arch/blackfin/mach-bf538/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf538/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES 64
11 11
12#define P_TMR2 (P_DONTCARE) 12#define P_TMR2 (P_DONTCARE)
13#define P_TMR1 (P_DONTCARE) 13#define P_TMR1 (P_DONTCARE)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 00:28:58 -0500