diff options
Diffstat (limited to 'arch/blackfin/mach-bf537')
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/cdefBF534.h | 14 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 8 |
2 files changed, 6 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h index fbeb35e14135..68ea8553c2c6 100644 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h | |||
| @@ -355,16 +355,10 @@ | |||
| 355 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) | 355 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) |
| 356 | 356 | ||
| 357 | /* DMA Traffic Control Registers */ | 357 | /* DMA Traffic Control Registers */ |
| 358 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | 358 | #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) |
| 359 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) | 359 | #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) |
| 360 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | 360 | #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) |
| 361 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) | 361 | #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) |
| 362 | |||
| 363 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
| 364 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | ||
| 365 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) | ||
| 366 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | ||
| 367 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) | ||
| 368 | 362 | ||
| 369 | /* DMA Controller */ | 363 | /* DMA Controller */ |
| 370 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | 364 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 8ca84edf3c38..b8c1b6fb81f4 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h | |||
| @@ -193,12 +193,8 @@ | |||
| 193 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | 193 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ |
| 194 | 194 | ||
| 195 | /* DMA Traffic Control Registers */ | 195 | /* DMA Traffic Control Registers */ |
| 196 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ | 196 | #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
| 197 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | 197 | #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ |
| 198 | |||
| 199 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
| 200 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
| 201 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
| 202 | 198 | ||
| 203 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ | 199 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ |
| 204 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | 200 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |