1 files changed, 0 insertions, 79 deletions

diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 0836bfdcc6c5..2c4ae466d4e9 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -478,85 +478,6 @@ ENTRY(_start_dma_code)
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
 
-ENTRY(_bfin_reset)
-        /* No more interrupts to be handled*/
-        CLI R6;
-        SSYNC;
-
-#if defined(CONFIG_MTD_M25P80)
-        /*
-         * The following code fix the SPI flash reboot issue,
-         * /CS signal of the chip which is using PF10 return to GPIO mode
-         */
-        p0.h = hi(PORTF_FER);
-        p0.l = lo(PORTF_FER);
-        r0.l = 0x0000;
-        w[p0] = r0.l;
-        SSYNC;
-
-        /* /CS return to high */
-        p0.h = hi(PORTFIO);
-        p0.l = lo(PORTFIO);
-        r0.l = 0xFFFF;
-        w[p0] = r0.l;
-        SSYNC;
-
-        /* Delay some time, This is necessary */
-        r1.h = 0;
-        r1.l = 0x400;
-        p1   = r1;
-        lsetup (.L_delay_lab1, .L_delay_lab1_end) lc1 = p1;
-.L_delay_lab1:
-        r0.h = 0;
-        r0.l = 0x8000;
-        p0   = r0;
-        lsetup (.L_delay_lab0, .L_delay_lab0_end) lc0 = p0;
-.L_delay_lab0:
-        nop;
-.L_delay_lab0_end:
-        nop;
-.L_delay_lab1_end:
-        nop;
-#endif
-
-        /* Clear the IMASK register */
-        p0.h = hi(IMASK);
-        p0.l = lo(IMASK);
-        r0 = 0x0;
-        [p0] = r0;
-
-        /* Clear the ILAT register */
-        p0.h = hi(ILAT);
-        p0.l = lo(ILAT);
-        r0 = [p0];
-        [p0] = r0;
-        SSYNC;
-
-        /* make sure SYSCR is set to use BMODE */
-        P0.h = hi(SYSCR);
-        P0.l = lo(SYSCR);
-        R0.l = 0x0;
-        W[P0] = R0.l;
-        SSYNC;
-
-        /* issue a system soft reset */
-        P1.h = hi(SWRST);
-        P1.l = lo(SWRST);
-        R1.l = 0x0007;
-        W[P1] = R1;
-        SSYNC;
-
-        /* clear system soft reset */
-        R0.l = 0x0000;
-        W[P0] = R0;
-        SSYNC;
-
-        /* issue core reset */
-        raise 1;
-
-        RTS;
-ENDPROC(_bfin_reset)
-
 .data
 
 /*