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-rw-r--r--arch/blackfin/mach-bf537/boards/Kconfig6
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537e.c12
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537u.c12
-rw-r--r--arch/blackfin/mach-bf537/boards/dnp5370.c418
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c12
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c4
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c18
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c12
-rw-r--r--arch/blackfin/mach-bf537/dma.c2
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h72
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h38
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h27
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF537.h5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h113
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF537.h5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/gpio.h4
-rw-r--r--arch/blackfin/mach-bf537/include/mach/pll.h58
19 files changed, 507 insertions, 326 deletions
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 44132fda63be..a44bf3a1816e 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -39,4 +39,10 @@ config CAMSIG_MINOTAUR
39 help 39 help
40 Board supply package for CSP Minotaur 40 Board supply package for CSP Minotaur
41 41
42config DNP5370
43 bool "SSV Dil/NetPC DNP/5370"
44 depends on (BF537)
45 help
46 Board supply package for DNP/5370 DIL64 module
47
42endchoice 48endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7e6aa4e5b205..fe42258fe1f4 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o 8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
9obj-$(CONFIG_PNAV10) += pnav10.o 9obj-$(CONFIG_PNAV10) += pnav10.o
10obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o 10obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
11obj-$(CONFIG_DNP5370) += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 836698c4ee54..2c776e188a94 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -373,7 +373,7 @@ static struct resource bfin_uart0_resources[] = {
373#endif 373#endif
374}; 374};
375 375
376unsigned short bfin_uart0_peripherals[] = { 376static unsigned short bfin_uart0_peripherals[] = {
377 P_UART0_TX, P_UART0_RX, 0 377 P_UART0_TX, P_UART0_RX, 0
378}; 378};
379 379
@@ -434,7 +434,7 @@ static struct resource bfin_uart1_resources[] = {
434#endif 434#endif
435}; 435};
436 436
437unsigned short bfin_uart1_peripherals[] = { 437static unsigned short bfin_uart1_peripherals[] = {
438 P_UART1_TX, P_UART1_RX, 0 438 P_UART1_TX, P_UART1_RX, 0
439}; 439};
440 440
@@ -545,9 +545,9 @@ static struct resource bfin_sport0_uart_resources[] = {
545 }, 545 },
546}; 546};
547 547
548unsigned short bfin_sport0_peripherals[] = { 548static unsigned short bfin_sport0_peripherals[] = {
549 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 549 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
550 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 550 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
551}; 551};
552 552
553static struct platform_device bfin_sport0_uart_device = { 553static struct platform_device bfin_sport0_uart_device = {
@@ -579,9 +579,9 @@ static struct resource bfin_sport1_uart_resources[] = {
579 }, 579 },
580}; 580};
581 581
582unsigned short bfin_sport1_peripherals[] = { 582static unsigned short bfin_sport1_peripherals[] = {
583 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 583 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
584 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 584 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
585}; 585};
586 586
587static struct platform_device bfin_sport1_uart_device = { 587static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index 2a85670273cb..085661175ec7 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
356 }, 356 },
357}; 357};
358 358
359unsigned short bfin_uart0_peripherals[] = { 359static unsigned short bfin_uart0_peripherals[] = {
360 P_UART0_TX, P_UART0_RX, 0 360 P_UART0_TX, P_UART0_RX, 0
361}; 361};
362 362
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
399 }, 399 },
400}; 400};
401 401
402unsigned short bfin_uart1_peripherals[] = { 402static unsigned short bfin_uart1_peripherals[] = {
403 P_UART1_TX, P_UART1_RX, 0 403 P_UART1_TX, P_UART1_RX, 0
404}; 404};
405 405
@@ -510,9 +510,9 @@ static struct resource bfin_sport0_uart_resources[] = {
510 }, 510 },
511}; 511};
512 512
513unsigned short bfin_sport0_peripherals[] = { 513static unsigned short bfin_sport0_peripherals[] = {
514 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 514 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
515 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 515 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
516}; 516};
517 517
518static struct platform_device bfin_sport0_uart_device = { 518static struct platform_device bfin_sport0_uart_device = {
@@ -544,9 +544,9 @@ static struct resource bfin_sport1_uart_resources[] = {
544 }, 544 },
545}; 545};
546 546
547unsigned short bfin_sport1_peripherals[] = { 547static unsigned short bfin_sport1_peripherals[] = {
548 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 548 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
549 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 549 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
550}; 550};
551 551
552static struct platform_device bfin_sport1_uart_device = { 552static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
new file mode 100644
index 000000000000..e1e9ea02ad89
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -0,0 +1,418 @@
1/*
2 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
3 *
4 * DIL module: http://www.dilnetpc.com/dnp0086.htm
5 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
6 *
7 * Copyright 2010 3ality Digital Systems
8 * Copyright 2005 National ICT Australia (NICTA)
9 * Copyright 2004-2006 Analog Devices Inc.
10 *
11 * Licensed under the GPL-2 or later.
12 */
13
14#include <linux/device.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/plat-ram.h>
22#include <linux/mtd/physmap.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/flash.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/i2c.h>
28#include <linux/spi/mmc_spi.h>
29#include <linux/phy.h>
30#include <asm/dma.h>
31#include <asm/bfin5xx_spi.h>
32#include <asm/reboot.h>
33#include <asm/portmux.h>
34#include <asm/dpmc.h>
35
36/*
37 * Name the Board for the /proc/cpuinfo
38 */
39const char bfin_board_name[] = "DNP/5370";
40#define FLASH_MAC 0x202f0000
41#define CONFIG_MTD_PHYSMAP_LEN 0x300000
42
43#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
44static struct platform_device rtc_device = {
45 .name = "rtc-bfin",
46 .id = -1,
47};
48#endif
49
50#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
51#include <linux/bfin_mac.h>
52static const unsigned short bfin_mac_peripherals[] = P_RMII0;
53
54static struct bfin_phydev_platform_data bfin_phydev_data[] = {
55 {
56 .addr = 1,
57 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
58 },
59};
60
61static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
62 .phydev_number = 1,
63 .phydev_data = bfin_phydev_data,
64 .phy_mode = PHY_INTERFACE_MODE_RMII,
65 .mac_peripherals = bfin_mac_peripherals,
66};
67
68static struct platform_device bfin_mii_bus = {
69 .name = "bfin_mii_bus",
70 .dev = {
71 .platform_data = &bfin_mii_bus_data,
72 }
73};
74
75static struct platform_device bfin_mac_device = {
76 .name = "bfin_mac",
77 .dev = {
78 .platform_data = &bfin_mii_bus,
79 }
80};
81#endif
82
83#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
84static struct mtd_partition asmb_flash_partitions[] = {
85 {
86 .name = "bootloader(nor)",
87 .size = 0x30000,
88 .offset = 0,
89 }, {
90 .name = "linux kernel and rootfs(nor)",
91 .size = 0x300000 - 0x30000 - 0x10000,
92 .offset = MTDPART_OFS_APPEND,
93 }, {
94 .name = "MAC address(nor)",
95 .size = 0x10000,
96 .offset = MTDPART_OFS_APPEND,
97 .mask_flags = MTD_WRITEABLE,
98 }
99};
100
101static struct physmap_flash_data asmb_flash_data = {
102 .width = 1,
103 .parts = asmb_flash_partitions,
104 .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
105};
106
107static struct resource asmb_flash_resource = {
108 .start = 0x20000000,
109 .end = 0x202fffff,
110 .flags = IORESOURCE_MEM,
111};
112
113/* 4 MB NOR flash attached to async memory banks 0-2,
114 * therefore only 3 MB visible.
115 */
116static struct platform_device asmb_flash_device = {
117 .name = "physmap-flash",
118 .id = 0,
119 .dev = {
120 .platform_data = &asmb_flash_data,
121 },
122 .num_resources = 1,
123 .resource = &asmb_flash_resource,
124};
125#endif
126
127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
128
129#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
130
131#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
132
133static int bfin_mmc_spi_init(struct device *dev,
134 irqreturn_t (*detect_int)(int, void *), void *data)
135{
136 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
137 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
138}
139
140static void bfin_mmc_spi_exit(struct device *dev, void *data)
141{
142 free_irq(MMC_SPI_CARD_DETECT_INT, data);
143}
144
145static struct bfin5xx_spi_chip mmc_spi_chip_info = {
146 .enable_dma = 0, /* use no dma transfer with this chip*/
147 .bits_per_word = 8,
148};
149
150static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
151 .init = bfin_mmc_spi_init,
152 .exit = bfin_mmc_spi_exit,
153 .detect_delay = 100, /* msecs */
154};
155#endif
156
157#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
158/* This mapping is for at45db642 it has 1056 page size,
159 * partition size and offset should be page aligned
160 */
161static struct mtd_partition bfin_spi_dataflash_partitions[] = {
162 {
163 .name = "JFFS2 dataflash(nor)",
164#ifdef CONFIG_MTD_PAGESIZE_1024
165 .offset = 0x40000,
166 .size = 0x7C0000,
167#else
168 .offset = 0x0,
169 .size = 0x840000,
170#endif
171 }
172};
173
174static struct flash_platform_data bfin_spi_dataflash_data = {
175 .name = "mtd_dataflash",
176 .parts = bfin_spi_dataflash_partitions,
177 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
178 .type = "mtd_dataflash",
179};
180
181static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
182 .enable_dma = 0, /* use no dma transfer with this chip*/
183 .bits_per_word = 8,
184};
185#endif
186
187static struct spi_board_info bfin_spi_board_info[] __initdata = {
188/* SD/MMC card reader at SPI bus */
189#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
190 {
191 .modalias = "mmc_spi",
192 .max_speed_hz = 20000000,
193 .bus_num = 0,
194 .chip_select = 1,
195 .platform_data = &bfin_mmc_spi_pdata,
196 .controller_data = &mmc_spi_chip_info,
197 .mode = SPI_MODE_3,
198 },
199#endif
200
201/* 8 Megabyte Atmel NOR flash chip at SPI bus */
202#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
203 {
204 .modalias = "mtd_dataflash",
205 .max_speed_hz = 16700000,
206 .bus_num = 0,
207 .chip_select = 2,
208 .platform_data = &bfin_spi_dataflash_data,
209 .controller_data = &spi_dataflash_chip_info,
210 .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
211 },
212#endif
213};
214
215/* SPI controller data */
216/* SPI (0) */
217static struct resource bfin_spi0_resource[] = {
218 [0] = {
219 .start = SPI0_REGBASE,
220 .end = SPI0_REGBASE + 0xFF,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = CH_SPI,
225 .end = CH_SPI,
226 .flags = IORESOURCE_DMA,
227 },
228 [2] = {
229 .start = IRQ_SPI,
230 .end = IRQ_SPI,
231 .flags = IORESOURCE_IRQ,
232 },
233};
234
235static struct bfin5xx_spi_master spi_bfin_master_info = {
236 .num_chipselect = 8,
237 .enable_dma = 1, /* master has the ability to do dma transfer */
238 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
239};
240
241static struct platform_device spi_bfin_master_device = {
242 .name = "bfin-spi",
243 .id = 0, /* Bus number */
244 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
245 .resource = bfin_spi0_resource,
246 .dev = {
247 .platform_data = &spi_bfin_master_info, /* Passed to driver */
248 },
249};
250#endif
251
252#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
253#ifdef CONFIG_SERIAL_BFIN_UART0
254static struct resource bfin_uart0_resources[] = {
255 {
256 .start = UART0_THR,
257 .end = UART0_GCTL+2,
258 .flags = IORESOURCE_MEM,
259 },
260 {
261 .start = IRQ_UART0_RX,
262 .end = IRQ_UART0_RX+1,
263 .flags = IORESOURCE_IRQ,
264 },
265 {
266 .start = IRQ_UART0_ERROR,
267 .end = IRQ_UART0_ERROR,
268 .flags = IORESOURCE_IRQ,
269 },
270 {
271 .start = CH_UART0_TX,
272 .end = CH_UART0_TX,
273 .flags = IORESOURCE_DMA,
274 },
275 {
276 .start = CH_UART0_RX,
277 .end = CH_UART0_RX,
278 .flags = IORESOURCE_DMA,
279 },
280};
281
282static unsigned short bfin_uart0_peripherals[] = {
283 P_UART0_TX, P_UART0_RX, 0
284};
285
286static struct platform_device bfin_uart0_device = {
287 .name = "bfin-uart",
288 .id = 0,
289 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
290 .resource = bfin_uart0_resources,
291 .dev = {
292 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
293 },
294};
295#endif
296
297#ifdef CONFIG_SERIAL_BFIN_UART1
298static struct resource bfin_uart1_resources[] = {
299 {
300 .start = UART1_THR,
301 .end = UART1_GCTL+2,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .start = IRQ_UART1_RX,
306 .end = IRQ_UART1_RX+1,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_UART1_ERROR,
311 .end = IRQ_UART1_ERROR,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = CH_UART1_TX,
316 .end = CH_UART1_TX,
317 .flags = IORESOURCE_DMA,
318 },
319 {
320 .start = CH_UART1_RX,
321 .end = CH_UART1_RX,
322 .flags = IORESOURCE_DMA,
323 },
324};
325
326static unsigned short bfin_uart1_peripherals[] = {
327 P_UART1_TX, P_UART1_RX, 0
328};
329
330static struct platform_device bfin_uart1_device = {
331 .name = "bfin-uart",
332 .id = 1,
333 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
334 .resource = bfin_uart1_resources,
335 .dev = {
336 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
337 },
338};
339#endif
340#endif
341
342#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
343static struct resource bfin_twi0_resource[] = {
344 [0] = {
345 .start = TWI0_REGBASE,
346 .end = TWI0_REGBASE + 0xff,
347 .flags = IORESOURCE_MEM,
348 },
349 [1] = {
350 .start = IRQ_TWI,
351 .end = IRQ_TWI,
352 .flags = IORESOURCE_IRQ,
353 },
354};
355
356static struct platform_device i2c_bfin_twi_device = {
357 .name = "i2c-bfin-twi",
358 .id = 0,
359 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
360 .resource = bfin_twi0_resource,
361};
362#endif
363
364static struct platform_device *dnp5370_devices[] __initdata = {
365
366#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
367#ifdef CONFIG_SERIAL_BFIN_UART0
368 &bfin_uart0_device,
369#endif
370#ifdef CONFIG_SERIAL_BFIN_UART1
371 &bfin_uart1_device,
372#endif
373#endif
374
375#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
376 &asmb_flash_device,
377#endif
378
379#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
380 &bfin_mii_bus,
381 &bfin_mac_device,
382#endif
383
384#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
385 &spi_bfin_master_device,
386#endif
387
388#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
389 &i2c_bfin_twi_device,
390#endif
391
392#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
393 &rtc_device,
394#endif
395
396};
397
398static int __init dnp5370_init(void)
399{
400 printk(KERN_INFO "DNP/5370: registering device resources\n");
401 platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
402 printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
403 ARRAY_SIZE(bfin_spi_board_info));
404 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
405 printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
406 return 0;
407}
408arch_initcall(dnp5370_init);
409
410/*
411 * Currently the MAC address is saved in Flash by U-Boot
412 */
413void bfin_get_ether_addr(char *addr)
414{
415 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
416 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
417}
418EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index 49800518412c..bfb3671a78da 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -263,7 +263,7 @@ static struct resource bfin_uart0_resources[] = {
263 }, 263 },
264}; 264};
265 265
266unsigned short bfin_uart0_peripherals[] = { 266static unsigned short bfin_uart0_peripherals[] = {
267 P_UART0_TX, P_UART0_RX, 0 267 P_UART0_TX, P_UART0_RX, 0
268}; 268};
269 269
@@ -306,7 +306,7 @@ static struct resource bfin_uart1_resources[] = {
306 }, 306 },
307}; 307};
308 308
309unsigned short bfin_uart1_peripherals[] = { 309static unsigned short bfin_uart1_peripherals[] = {
310 P_UART1_TX, P_UART1_RX, 0 310 P_UART1_TX, P_UART1_RX, 0
311}; 311};
312 312
@@ -419,9 +419,9 @@ static struct resource bfin_sport0_uart_resources[] = {
419 }, 419 },
420}; 420};
421 421
422unsigned short bfin_sport0_peripherals[] = { 422static unsigned short bfin_sport0_peripherals[] = {
423 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 423 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
424 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 424 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
425}; 425};
426 426
427static struct platform_device bfin_sport0_uart_device = { 427static struct platform_device bfin_sport0_uart_device = {
@@ -453,9 +453,9 @@ static struct resource bfin_sport1_uart_resources[] = {
453 }, 453 },
454}; 454};
455 455
456unsigned short bfin_sport1_peripherals[] = { 456static unsigned short bfin_sport1_peripherals[] = {
457 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 457 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
458 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 458 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
459}; 459};
460 460
461static struct platform_device bfin_sport1_uart_device = { 461static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index b95807894e25..9389f03e3b0a 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -367,7 +367,7 @@ static struct resource bfin_uart0_resources[] = {
367 }, 367 },
368}; 368};
369 369
370unsigned short bfin_uart0_peripherals[] = { 370static unsigned short bfin_uart0_peripherals[] = {
371 P_UART0_TX, P_UART0_RX, 0 371 P_UART0_TX, P_UART0_RX, 0
372}; 372};
373 373
@@ -410,7 +410,7 @@ static struct resource bfin_uart1_resources[] = {
410 }, 410 },
411}; 411};
412 412
413unsigned short bfin_uart1_peripherals[] = { 413static unsigned short bfin_uart1_peripherals[] = {
414 P_UART1_TX, P_UART1_RX, 0 414 P_UART1_TX, P_UART1_RX, 0
415}; 415};
416 416
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3aa344ce8e52..2c69785a7bbe 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -289,7 +289,7 @@ static struct platform_device isp1362_hcd_device = {
289#endif 289#endif
290 290
291#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) 291#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
292unsigned short bfin_can_peripherals[] = { 292static unsigned short bfin_can_peripherals[] = {
293 P_CAN0_RX, P_CAN0_TX, 0 293 P_CAN0_RX, P_CAN0_TX, 0
294}; 294};
295 295
@@ -693,7 +693,7 @@ static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
693#endif 693#endif
694 694
695#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE) 695#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
696unsigned short ad2s120x_platform_data[] = { 696static unsigned short ad2s120x_platform_data[] = {
697 /* used as SAMPLE and RDVEL */ 697 /* used as SAMPLE and RDVEL */
698 GPIO_PF5, GPIO_PF6, 0 698 GPIO_PF5, GPIO_PF6, 0
699}; 699};
@@ -705,7 +705,7 @@ static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
705#endif 705#endif
706 706
707#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE) 707#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
708unsigned short ad2s1210_platform_data[] = { 708static unsigned short ad2s1210_platform_data[] = {
709 /* use as SAMPLE, A0, A1 */ 709 /* use as SAMPLE, A0, A1 */
710 GPIO_PF7, GPIO_PF8, GPIO_PF9, 710 GPIO_PF7, GPIO_PF8, GPIO_PF9,
711# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT) 711# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
@@ -1717,7 +1717,7 @@ static struct resource bfin_uart0_resources[] = {
1717#endif 1717#endif
1718}; 1718};
1719 1719
1720unsigned short bfin_uart0_peripherals[] = { 1720static unsigned short bfin_uart0_peripherals[] = {
1721 P_UART0_TX, P_UART0_RX, 0 1721 P_UART0_TX, P_UART0_RX, 0
1722}; 1722};
1723 1723
@@ -1760,7 +1760,7 @@ static struct resource bfin_uart1_resources[] = {
1760 }, 1760 },
1761}; 1761};
1762 1762
1763unsigned short bfin_uart1_peripherals[] = { 1763static unsigned short bfin_uart1_peripherals[] = {
1764 P_UART1_TX, P_UART1_RX, 0 1764 P_UART1_TX, P_UART1_RX, 0
1765}; 1765};
1766 1766
@@ -2447,9 +2447,9 @@ static struct resource bfin_sport0_uart_resources[] = {
2447 }, 2447 },
2448}; 2448};
2449 2449
2450unsigned short bfin_sport0_peripherals[] = { 2450static unsigned short bfin_sport0_peripherals[] = {
2451 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 2451 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
2452 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 2452 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
2453}; 2453};
2454 2454
2455static struct platform_device bfin_sport0_uart_device = { 2455static struct platform_device bfin_sport0_uart_device = {
@@ -2481,9 +2481,9 @@ static struct resource bfin_sport1_uart_resources[] = {
2481 }, 2481 },
2482}; 2482};
2483 2483
2484unsigned short bfin_sport1_peripherals[] = { 2484static unsigned short bfin_sport1_peripherals[] = {
2485 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 2485 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
2486 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 2486 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
2487}; 2487};
2488 2488
2489static struct platform_device bfin_sport1_uart_device = { 2489static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 31498add1a42..0761b201abca 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
356 }, 356 },
357}; 357};
358 358
359unsigned short bfin_uart0_peripherals[] = { 359static unsigned short bfin_uart0_peripherals[] = {
360 P_UART0_TX, P_UART0_RX, 0 360 P_UART0_TX, P_UART0_RX, 0
361}; 361};
362 362
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
399 }, 399 },
400}; 400};
401 401
402unsigned short bfin_uart1_peripherals[] = { 402static unsigned short bfin_uart1_peripherals[] = {
403 P_UART1_TX, P_UART1_RX, 0 403 P_UART1_TX, P_UART1_RX, 0
404}; 404};
405 405
@@ -512,9 +512,9 @@ static struct resource bfin_sport0_uart_resources[] = {
512 }, 512 },
513}; 513};
514 514
515unsigned short bfin_sport0_peripherals[] = { 515static unsigned short bfin_sport0_peripherals[] = {
516 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 516 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
517 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 517 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
518}; 518};
519 519
520static struct platform_device bfin_sport0_uart_device = { 520static struct platform_device bfin_sport0_uart_device = {
@@ -546,9 +546,9 @@ static struct resource bfin_sport1_uart_resources[] = {
546 }, 546 },
547}; 547};
548 548
549unsigned short bfin_sport1_peripherals[] = { 549static unsigned short bfin_sport1_peripherals[] = {
550 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 550 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
551 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 551 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
552}; 552};
553 553
554static struct platform_device bfin_sport1_uart_device = { 554static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
index 5c8c4ed517bb..5c62e99c9fac 100644
--- a/arch/blackfin/mach-bf537/dma.c
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -11,7 +11,7 @@
11#include <asm/blackfin.h> 11#include <asm/blackfin.h>
12#include <asm/dma.h> 12#include <asm/dma.h>
13 13
14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index 635c91c526a3..3e955dba8951 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,49 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 int cts_pin;
79 int rts_pin;
80#endif
81};
82
83/* The hardware clears the LSR bits upon read, so we need to cache
84 * some of the more fun bits in software so they don't get lost
85 * when checking the LSR in other code paths (TX).
86 */
87static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
88{
89 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
90 uart->lsr |= (lsr & (BI|FE|PE|OE));
91 return lsr | uart->lsr;
92}
93
94static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
95{
96 uart->lsr = 0;
97 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
98}
99
100struct bfin_serial_res { 30struct bfin_serial_res {
101 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
102 int uart_irq; 32 int uart_irq;
@@ -145,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
145}; 75};
146 76
147#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index a12d4b6a221d..baa096fc724a 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _MACH_BLACKFIN_H_ 7#ifndef _MACH_BLACKFIN_H_
@@ -10,34 +10,24 @@
10#define BF537_FAMILY 10#define BF537_FAMILY
11 11
12#include "bf537.h" 12#include "bf537.h"
13#include "defBF534.h"
14#include "anomaly.h" 13#include "anomaly.h"
15 14
15#include <asm/def_LPBlackfin.h>
16#ifdef CONFIG_BF534
17# include "defBF534.h"
18#endif
16#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 19#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
17#include "defBF537.h" 20# include "defBF537.h"
18#endif 21#endif
19 22
20#if !defined(__ASSEMBLY__) 23#if !defined(__ASSEMBLY__)
21#include "cdefBF534.h" 24# include <asm/cdef_LPBlackfin.h>
22 25# ifdef CONFIG_BF534
23#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 26# include "cdefBF534.h"
24#include "cdefBF537.h" 27# endif
28# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
29# include "cdefBF537.h"
30# endif
25#endif 31#endif
26#endif
27
28#define BFIN_UART_NR_PORTS 2
29
30#define OFFSET_THR 0x00 /* Transmit Holding register */
31#define OFFSET_RBR 0x00 /* Receive Buffer register */
32#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
33#define OFFSET_IER 0x04 /* Interrupt Enable Register */
34#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
35#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
36#define OFFSET_LCR 0x0C /* Line Control Register */
37#define OFFSET_MCR 0x10 /* Modem Control Register */
38#define OFFSET_LSR 0x14 /* Line Status Register */
39#define OFFSET_MSR 0x18 /* Modem Status Register */
40#define OFFSET_SCR 0x1C /* SCR Scratch Register */
41#define OFFSET_GCTL 0x24 /* Global Control Register */
42 32
43#endif 33#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index fbeb35e14135..563ede907336 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF534_H 7#ifndef _CDEF_BF534_H
8#define _CDEF_BF534_H 8#define _CDEF_BF534_H
9 9
10#include <asm/blackfin.h>
11
12/* Include all Core registers and bit definitions */
13#include "defBF534.h"
14
15/* Include core specific register pointer definitions */
16#include <asm/cdef_LPBlackfin.h>
17
18/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 10/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
19#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
20#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 12#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
@@ -355,16 +347,10 @@
355#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) 347#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
356 348
357/* DMA Traffic Control Registers */ 349/* DMA Traffic Control Registers */
358#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) 350#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
359#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) 351#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
360#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) 352#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
361#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) 353#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
362
363/* Alternate deprecated register names (below) provided for backwards code compatibility */
364#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
365#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
366#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
367#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
368 354
369/* DMA Controller */ 355/* DMA Controller */
370#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 356#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
@@ -1747,7 +1733,4 @@
1747#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) 1733#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1748#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) 1734#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1749 1735
1750/* These need to be last due to the cdef/linux inter-dependencies */
1751#include <asm/irq.h>
1752
1753#endif /* _CDEF_BF534_H */ 1736#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
index 9363c3990421..19ec21ea150a 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -10,9 +10,6 @@
10/* Include MMRs Common to BF534 */ 10/* Include MMRs Common to BF534 */
11#include "cdefBF534.h" 11#include "cdefBF534.h"
12 12
13/* Include all Core registers and bit definitions */
14#include "defBF537.h"
15
16/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ 13/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
17/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 14/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
18#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) 15#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 0323e6bacdae..725bb35f3aaa 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _DEF_BF534_H 7#ifndef _DEF_BF534_H
8#define _DEF_BF534_H 8#define _DEF_BF534_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/************************************************************************************ 10/************************************************************************************
14** System MMR Register Map 11** System MMR Register Map
15*************************************************************************************/ 12*************************************************************************************/
@@ -193,12 +190,8 @@
193#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 190#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
194 191
195/* DMA Traffic Control Registers */ 192/* DMA Traffic Control Registers */
196#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 193#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
197#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 194#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
198
199/* Alternate deprecated register names (below) provided for backwards code compatibility */
200#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
201#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
202 195
203/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 196/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
204#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 197#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -1029,48 +1022,6 @@
1029#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1022#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1030#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1023#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1031 1024
1032/* ************** UART CONTROLLER MASKS *************************/
1033/* UARTx_LCR Masks */
1034#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1035#define STB 0x04 /* Stop Bits */
1036#define PEN 0x08 /* Parity Enable */
1037#define EPS 0x10 /* Even Parity Select */
1038#define STP 0x20 /* Stick Parity */
1039#define SB 0x40 /* Set Break */
1040#define DLAB 0x80 /* Divisor Latch Access */
1041
1042/* UARTx_MCR Mask */
1043#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1044#define LOOP_ENA_P 0x04
1045/* UARTx_LSR Masks */
1046#define DR 0x01 /* Data Ready */
1047#define OE 0x02 /* Overrun Error */
1048#define PE 0x04 /* Parity Error */
1049#define FE 0x08 /* Framing Error */
1050#define BI 0x10 /* Break Interrupt */
1051#define THRE 0x20 /* THR Empty */
1052#define TEMT 0x40 /* TSR and UART_THR Empty */
1053
1054/* UARTx_IER Masks */
1055#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1056#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1057#define ELSI 0x04 /* Enable RX Status Interrupt */
1058
1059/* UARTx_IIR Masks */
1060#define NINT 0x01 /* Pending Interrupt */
1061#define IIR_TX_READY 0x02 /* UART_THR empty */
1062#define IIR_RX_READY 0x04 /* Receive data ready */
1063#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1064#define IIR_STATUS 0x06
1065
1066/* UARTx_GCTL Masks */
1067#define UCEN 0x01 /* Enable UARTx Clocks */
1068#define IREN 0x02 /* Enable IrDA Mode */
1069#define TPOLC 0x04 /* IrDA TX Polarity Change */
1070#define RPOLC 0x08 /* IrDA RX Polarity Change */
1071#define FPE 0x10 /* Force Parity Error On Transmit */
1072#define FFE 0x20 /* Force Framing Error On Transmit */
1073
1074/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 1025/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1075/* TIMER_ENABLE Masks */ 1026/* TIMER_ENABLE Masks */
1076#define TIMEN0 0x0001 /* Enable Timer 0 */ 1027#define TIMEN0 0x0001 /* Enable Timer 0 */
@@ -1141,62 +1092,6 @@
1141#define EMU_RUN 0x0200 /* Emulation Behavior Select */ 1092#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1142#define ERR_TYP 0xC000 /* Error Type */ 1093#define ERR_TYP 0xC000 /* Error Type */
1143 1094
1144/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1145/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1146/* Port F Masks */
1147#define PF0 0x0001
1148#define PF1 0x0002
1149#define PF2 0x0004
1150#define PF3 0x0008
1151#define PF4 0x0010
1152#define PF5 0x0020
1153#define PF6 0x0040
1154#define PF7 0x0080
1155#define PF8 0x0100
1156#define PF9 0x0200
1157#define PF10 0x0400
1158#define PF11 0x0800
1159#define PF12 0x1000
1160#define PF13 0x2000
1161#define PF14 0x4000
1162#define PF15 0x8000
1163
1164/* Port G Masks */
1165#define PG0 0x0001
1166#define PG1 0x0002
1167#define PG2 0x0004
1168#define PG3 0x0008
1169#define PG4 0x0010
1170#define PG5 0x0020
1171#define PG6 0x0040
1172#define PG7 0x0080
1173#define PG8 0x0100
1174#define PG9 0x0200
1175#define PG10 0x0400
1176#define PG11 0x0800
1177#define PG12 0x1000
1178#define PG13 0x2000
1179#define PG14 0x4000
1180#define PG15 0x8000
1181
1182/* Port H Masks */
1183#define PH0 0x0001
1184#define PH1 0x0002
1185#define PH2 0x0004
1186#define PH3 0x0008
1187#define PH4 0x0010
1188#define PH5 0x0020
1189#define PH6 0x0040
1190#define PH7 0x0080
1191#define PH8 0x0100
1192#define PH9 0x0200
1193#define PH10 0x0400
1194#define PH11 0x0800
1195#define PH12 0x1000
1196#define PH13 0x2000
1197#define PH14 0x4000
1198#define PH15 0x8000
1199
1200/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ 1095/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1201/* EBIU_AMGCTL Masks */ 1096/* EBIU_AMGCTL Masks */
1202#define AMCKEN 0x0001 /* Enable CLKOUT */ 1097#define AMCKEN 0x0001 /* Enable CLKOUT */
@@ -1523,7 +1418,7 @@
1523#define SADD_LEN 0x0002 /* Slave Address Length */ 1418#define SADD_LEN 0x0002 /* Slave Address Length */
1524#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 1419#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1525#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ 1420#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1526#define GEN 0x0010 /* General Call Adrress Matching Enabled */ 1421#define GEN 0x0010 /* General Call Address Matching Enabled */
1527 1422
1528/* TWI_SLAVE_STAT Masks */ 1423/* TWI_SLAVE_STAT Masks */
1529#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 1424#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
index 8cb5d5cf0c94..3d471d752684 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _DEF_BF537_H 7#ifndef _DEF_BF537_H
8#define _DEF_BF537_H 8#define _DEF_BF537_H
9 9
10/* Include all Core registers and bit definitions*/
11#include <asm/cdef_LPBlackfin.h>
12
13/* Include all MMR and bit defines common to BF534 */ 10/* Include all MMR and bit defines common to BF534 */
14#include "defBF534.h" 11#include "defBF534.h"
15 12
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf537/include/mach/gpio.h
@@ -62,4 +62,8 @@
62#define PORT_G GPIO_PG0 62#define PORT_G GPIO_PG0
63#define PORT_H GPIO_PH0 63#define PORT_H GPIO_PH0
64 64
65#include <mach-common/ports-f.h>
66#include <mach-common/ports-g.h>
67#include <mach-common/ports-h.h>
68
65#endif /* _MACH_GPIO_H_ */ 69#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -1,57 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 08:51:16 -0500