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-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h72
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h38
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h27
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF537.h5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h111
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF537.h5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/gpio.h4
-rw-r--r--arch/blackfin/mach-bf537/include/mach/pll.h58
9 files changed, 45 insertions, 289 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index 635c91c526a3..3e955dba8951 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,49 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 int cts_pin;
79 int rts_pin;
80#endif
81};
82
83/* The hardware clears the LSR bits upon read, so we need to cache
84 * some of the more fun bits in software so they don't get lost
85 * when checking the LSR in other code paths (TX).
86 */
87static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
88{
89 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
90 uart->lsr |= (lsr & (BI|FE|PE|OE));
91 return lsr | uart->lsr;
92}
93
94static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
95{
96 uart->lsr = 0;
97 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
98}
99
100struct bfin_serial_res { 30struct bfin_serial_res {
101 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
102 int uart_irq; 32 int uart_irq;
@@ -145,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
145}; 75};
146 76
147#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index a12d4b6a221d..baa096fc724a 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _MACH_BLACKFIN_H_ 7#ifndef _MACH_BLACKFIN_H_
@@ -10,34 +10,24 @@
10#define BF537_FAMILY 10#define BF537_FAMILY
11 11
12#include "bf537.h" 12#include "bf537.h"
13#include "defBF534.h"
14#include "anomaly.h" 13#include "anomaly.h"
15 14
15#include <asm/def_LPBlackfin.h>
16#ifdef CONFIG_BF534
17# include "defBF534.h"
18#endif
16#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 19#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
17#include "defBF537.h" 20# include "defBF537.h"
18#endif 21#endif
19 22
20#if !defined(__ASSEMBLY__) 23#if !defined(__ASSEMBLY__)
21#include "cdefBF534.h" 24# include <asm/cdef_LPBlackfin.h>
22 25# ifdef CONFIG_BF534
23#if defined(CONFIG_BF537) || defined(CONFIG_BF536) 26# include "cdefBF534.h"
24#include "cdefBF537.h" 27# endif
28# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
29# include "cdefBF537.h"
30# endif
25#endif 31#endif
26#endif
27
28#define BFIN_UART_NR_PORTS 2
29
30#define OFFSET_THR 0x00 /* Transmit Holding register */
31#define OFFSET_RBR 0x00 /* Receive Buffer register */
32#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
33#define OFFSET_IER 0x04 /* Interrupt Enable Register */
34#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
35#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
36#define OFFSET_LCR 0x0C /* Line Control Register */
37#define OFFSET_MCR 0x10 /* Modem Control Register */
38#define OFFSET_LSR 0x14 /* Line Status Register */
39#define OFFSET_MSR 0x18 /* Modem Status Register */
40#define OFFSET_SCR 0x1C /* SCR Scratch Register */
41#define OFFSET_GCTL 0x24 /* Global Control Register */
42 32
43#endif 33#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index fbeb35e14135..563ede907336 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF534_H 7#ifndef _CDEF_BF534_H
8#define _CDEF_BF534_H 8#define _CDEF_BF534_H
9 9
10#include <asm/blackfin.h>
11
12/* Include all Core registers and bit definitions */
13#include "defBF534.h"
14
15/* Include core specific register pointer definitions */
16#include <asm/cdef_LPBlackfin.h>
17
18/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 10/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
19#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 11#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
20#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 12#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
@@ -355,16 +347,10 @@
355#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) 347#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
356 348
357/* DMA Traffic Control Registers */ 349/* DMA Traffic Control Registers */
358#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) 350#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
359#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) 351#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
360#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) 352#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
361#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) 353#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
362
363/* Alternate deprecated register names (below) provided for backwards code compatibility */
364#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
365#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
366#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
367#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
368 354
369/* DMA Controller */ 355/* DMA Controller */
370#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 356#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
@@ -1747,7 +1733,4 @@
1747#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) 1733#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1748#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) 1734#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1749 1735
1750/* These need to be last due to the cdef/linux inter-dependencies */
1751#include <asm/irq.h>
1752
1753#endif /* _CDEF_BF534_H */ 1736#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
index 9363c3990421..19ec21ea150a 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
@@ -10,9 +10,6 @@
10/* Include MMRs Common to BF534 */ 10/* Include MMRs Common to BF534 */
11#include "cdefBF534.h" 11#include "cdefBF534.h"
12 12
13/* Include all Core registers and bit definitions */
14#include "defBF537.h"
15
16/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ 13/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
17/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 14/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
18#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) 15#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 0323e6bacdae..32529a03b266 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _DEF_BF534_H 7#ifndef _DEF_BF534_H
8#define _DEF_BF534_H 8#define _DEF_BF534_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/************************************************************************************ 10/************************************************************************************
14** System MMR Register Map 11** System MMR Register Map
15*************************************************************************************/ 12*************************************************************************************/
@@ -193,12 +190,8 @@
193#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 190#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
194 191
195/* DMA Traffic Control Registers */ 192/* DMA Traffic Control Registers */
196#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 193#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
197#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 194#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
198
199/* Alternate deprecated register names (below) provided for backwards code compatibility */
200#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
201#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
202 195
203/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 196/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
204#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 197#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -1029,48 +1022,6 @@
1029#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1022#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1030#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1023#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1031 1024
1032/* ************** UART CONTROLLER MASKS *************************/
1033/* UARTx_LCR Masks */
1034#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1035#define STB 0x04 /* Stop Bits */
1036#define PEN 0x08 /* Parity Enable */
1037#define EPS 0x10 /* Even Parity Select */
1038#define STP 0x20 /* Stick Parity */
1039#define SB 0x40 /* Set Break */
1040#define DLAB 0x80 /* Divisor Latch Access */
1041
1042/* UARTx_MCR Mask */
1043#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1044#define LOOP_ENA_P 0x04
1045/* UARTx_LSR Masks */
1046#define DR 0x01 /* Data Ready */
1047#define OE 0x02 /* Overrun Error */
1048#define PE 0x04 /* Parity Error */
1049#define FE 0x08 /* Framing Error */
1050#define BI 0x10 /* Break Interrupt */
1051#define THRE 0x20 /* THR Empty */
1052#define TEMT 0x40 /* TSR and UART_THR Empty */
1053
1054/* UARTx_IER Masks */
1055#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1056#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1057#define ELSI 0x04 /* Enable RX Status Interrupt */
1058
1059/* UARTx_IIR Masks */
1060#define NINT 0x01 /* Pending Interrupt */
1061#define IIR_TX_READY 0x02 /* UART_THR empty */
1062#define IIR_RX_READY 0x04 /* Receive data ready */
1063#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1064#define IIR_STATUS 0x06
1065
1066/* UARTx_GCTL Masks */
1067#define UCEN 0x01 /* Enable UARTx Clocks */
1068#define IREN 0x02 /* Enable IrDA Mode */
1069#define TPOLC 0x04 /* IrDA TX Polarity Change */
1070#define RPOLC 0x08 /* IrDA RX Polarity Change */
1071#define FPE 0x10 /* Force Parity Error On Transmit */
1072#define FFE 0x20 /* Force Framing Error On Transmit */
1073
1074/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 1025/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1075/* TIMER_ENABLE Masks */ 1026/* TIMER_ENABLE Masks */
1076#define TIMEN0 0x0001 /* Enable Timer 0 */ 1027#define TIMEN0 0x0001 /* Enable Timer 0 */
@@ -1141,62 +1092,6 @@
1141#define EMU_RUN 0x0200 /* Emulation Behavior Select */ 1092#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1142#define ERR_TYP 0xC000 /* Error Type */ 1093#define ERR_TYP 0xC000 /* Error Type */
1143 1094
1144/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1145/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1146/* Port F Masks */
1147#define PF0 0x0001
1148#define PF1 0x0002
1149#define PF2 0x0004
1150#define PF3 0x0008
1151#define PF4 0x0010
1152#define PF5 0x0020
1153#define PF6 0x0040
1154#define PF7 0x0080
1155#define PF8 0x0100
1156#define PF9 0x0200
1157#define PF10 0x0400
1158#define PF11 0x0800
1159#define PF12 0x1000
1160#define PF13 0x2000
1161#define PF14 0x4000
1162#define PF15 0x8000
1163
1164/* Port G Masks */
1165#define PG0 0x0001
1166#define PG1 0x0002
1167#define PG2 0x0004
1168#define PG3 0x0008
1169#define PG4 0x0010
1170#define PG5 0x0020
1171#define PG6 0x0040
1172#define PG7 0x0080
1173#define PG8 0x0100
1174#define PG9 0x0200
1175#define PG10 0x0400
1176#define PG11 0x0800
1177#define PG12 0x1000
1178#define PG13 0x2000
1179#define PG14 0x4000
1180#define PG15 0x8000
1181
1182/* Port H Masks */
1183#define PH0 0x0001
1184#define PH1 0x0002
1185#define PH2 0x0004
1186#define PH3 0x0008
1187#define PH4 0x0010
1188#define PH5 0x0020
1189#define PH6 0x0040
1190#define PH7 0x0080
1191#define PH8 0x0100
1192#define PH9 0x0200
1193#define PH10 0x0400
1194#define PH11 0x0800
1195#define PH12 0x1000
1196#define PH13 0x2000
1197#define PH14 0x4000
1198#define PH15 0x8000
1199
1200/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ 1095/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1201/* EBIU_AMGCTL Masks */ 1096/* EBIU_AMGCTL Masks */
1202#define AMCKEN 0x0001 /* Enable CLKOUT */ 1097#define AMCKEN 0x0001 /* Enable CLKOUT */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
index 8cb5d5cf0c94..3d471d752684 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2005-2008 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,9 +7,6 @@
7#ifndef _DEF_BF537_H 7#ifndef _DEF_BF537_H
8#define _DEF_BF537_H 8#define _DEF_BF537_H
9 9
10/* Include all Core registers and bit definitions*/
11#include <asm/cdef_LPBlackfin.h>
12
13/* Include all MMR and bit defines common to BF534 */ 10/* Include all MMR and bit defines common to BF534 */
14#include "defBF534.h" 11#include "defBF534.h"
15 12
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf537/include/mach/gpio.h
@@ -62,4 +62,8 @@
62#define PORT_G GPIO_PG0 62#define PORT_G GPIO_PG0
63#define PORT_H GPIO_PH0 63#define PORT_H GPIO_PH0
64 64
65#include <mach-common/ports-f.h>
66#include <mach-common/ports-g.h>
67#include <mach-common/ports-h.h>
68
65#endif /* _MACH_GPIO_H_ */ 69#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -1,57 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
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