1 files changed, 3 insertions, 108 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 0323e6bacdae..32529a03b266 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
 *
 * Licensed under the ADI BSD license or the GPL-2 (or later)
 */
@@ -7,9 +7,6 @@
 #ifndef _DEF_BF534_H
 #define _DEF_BF534_H
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
 /************************************************************************************
 ** System MMR Register Map
 *************************************************************************************/
@@ -193,12 +190,8 @@
 #define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
 /* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMAC_TC_PER                     0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
+#define DMAC_TC_CNT                     0xFFC00B10      /* Traffic Control Current Counts Register      */
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
 #define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
@@ -1029,48 +1022,6 @@
 #define IWR_ENABLE(x)   (1 << ((x)&0x1F))       /* Wakeup Enable Peripheral #x          */
 #define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select   */
-#define STB                     0x04    /* Stop Bits                    */
-#define PEN                     0x08    /* Parity Enable                */
-#define EPS                     0x10    /* Even Parity Select   */
-#define STP                     0x20    /* Stick Parity                 */
-#define SB                      0x40    /* Set Break                    */
-#define DLAB            0x80    /* Divisor Latch Access */
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA                0x10    /* Loopback Mode Enable         */
-#define LOOP_ENA_P      0x04
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01    /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02    /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04    /* Enable RX Status Interrupt                           */
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01    /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01    /* Enable UARTx Clocks                          */
-#define IREN            0x02    /* Enable IrDA Mode                                     */
-#define TPOLC           0x04    /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08    /* IrDA RX Polarity Change                      */
-#define FPE                     0x10    /* Force Parity Error On Transmit       */
-#define FFE                     0x20    /* Force Framing Error On Transmit      */
 /*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
 /* TIMER_ENABLE Masks                                                                                                   */
 #define TIMEN0                  0x0001  /* Enable Timer 0                                       */
@@ -1141,62 +1092,6 @@
 #define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
 #define ERR_TYP                 0xC000  /* Error Type                                                   */
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
 /* EBIU_AMGCTL Masks                                                                                                                                    */
 #define AMCKEN                  0x0001  /* Enable CLKOUT                                                                        */

diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 0323e6bacdae..32529a03b266 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,5 +1,5 @@
1	/*	1	/*
2	* Copyright 2005-2008 Analog Devices Inc.	2	* Copyright 2005-2010 Analog Devices Inc.
3	*	3	*
4	* Licensed under the ADI BSD license or the GPL-2 (or later)	4	* Licensed under the ADI BSD license or the GPL-2 (or later)
5	*/	5	*/
@@ -7,9 +7,6 @@
7	#ifndef _DEF_BF534_H	7	#ifndef _DEF_BF534_H
8	#define _DEF_BF534_H	8	#define _DEF_BF534_H
9		9
10	/* Include all Core registers and bit definitions */
11	#include <asm/def_LPBlackfin.h>
12
13	/************************************************************************************	10	/************************************************************************************
14	** System MMR Register Map	11	** System MMR Register Map
15	*************************************************************************************/	12	*************************************************************************************/
@@ -193,12 +190,8 @@
193	#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */	190	#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
194		191
195	/* DMA Traffic Control Registers */	192	/* DMA Traffic Control Registers */
196	#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */	193	#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
197	#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */	194	#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
198
199	/* Alternate deprecated register names (below) provided for backwards code compatibility */
200	#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
201	#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
202		195
203	/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */	196	/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
204	#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */	197	#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -1029,48 +1022,6 @@
1029	#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */	1022	#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1030	#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */	1023	#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1031		1024
1032	/* ************ UART CONTROLLER MASKS ***********************/
1033	/* UARTx_LCR Masks */
1034	#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1035	#define STB 0x04 /* Stop Bits */
1036	#define PEN 0x08 /* Parity Enable */
1037	#define EPS 0x10 /* Even Parity Select */
1038	#define STP 0x20 /* Stick Parity */
1039	#define SB 0x40 /* Set Break */
1040	#define DLAB 0x80 /* Divisor Latch Access */
1041
1042	/* UARTx_MCR Mask */
1043	#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1044	#define LOOP_ENA_P 0x04
1045	/* UARTx_LSR Masks */
1046	#define DR 0x01 /* Data Ready */
1047	#define OE 0x02 /* Overrun Error */
1048	#define PE 0x04 /* Parity Error */
1049	#define FE 0x08 /* Framing Error */
1050	#define BI 0x10 /* Break Interrupt */
1051	#define THRE 0x20 /* THR Empty */
1052	#define TEMT 0x40 /* TSR and UART_THR Empty */
1053
1054	/* UARTx_IER Masks */
1055	#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1056	#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1057	#define ELSI 0x04 /* Enable RX Status Interrupt */
1058
1059	/* UARTx_IIR Masks */
1060	#define NINT 0x01 /* Pending Interrupt */
1061	#define IIR_TX_READY 0x02 /* UART_THR empty */
1062	#define IIR_RX_READY 0x04 /* Receive data ready */
1063	#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1064	#define IIR_STATUS 0x06
1065
1066	/* UARTx_GCTL Masks */
1067	#define UCEN 0x01 /* Enable UARTx Clocks */
1068	#define IREN 0x02 /* Enable IrDA Mode */
1069	#define TPOLC 0x04 /* IrDA TX Polarity Change */
1070	#define RPOLC 0x08 /* IrDA RX Polarity Change */
1071	#define FPE 0x10 /* Force Parity Error On Transmit */
1072	#define FFE 0x20 /* Force Framing Error On Transmit */
1073
1074	/* ************** GENERAL PURPOSE TIMER MASKS ********************/	1025	/* ************** GENERAL PURPOSE TIMER MASKS ********************/
1075	/* TIMER_ENABLE Masks */	1026	/* TIMER_ENABLE Masks */
1076	#define TIMEN0 0x0001 /* Enable Timer 0 */	1027	#define TIMEN0 0x0001 /* Enable Timer 0 */
@@ -1141,62 +1092,6 @@
1141	#define EMU_RUN 0x0200 /* Emulation Behavior Select */	1092	#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1142	#define ERR_TYP 0xC000 /* Error Type */	1093	#define ERR_TYP 0xC000 /* Error Type */
1143		1094
1144	/* **************** GPIO PORTS F, G, H MASKS *********************/
1145	/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1146	/* Port F Masks */
1147	#define PF0 0x0001
1148	#define PF1 0x0002
1149	#define PF2 0x0004
1150	#define PF3 0x0008
1151	#define PF4 0x0010
1152	#define PF5 0x0020
1153	#define PF6 0x0040
1154	#define PF7 0x0080
1155	#define PF8 0x0100
1156	#define PF9 0x0200
1157	#define PF10 0x0400
1158	#define PF11 0x0800
1159	#define PF12 0x1000
1160	#define PF13 0x2000
1161	#define PF14 0x4000
1162	#define PF15 0x8000
1163
1164	/* Port G Masks */
1165	#define PG0 0x0001
1166	#define PG1 0x0002
1167	#define PG2 0x0004
1168	#define PG3 0x0008
1169	#define PG4 0x0010
1170	#define PG5 0x0020
1171	#define PG6 0x0040
1172	#define PG7 0x0080
1173	#define PG8 0x0100
1174	#define PG9 0x0200
1175	#define PG10 0x0400
1176	#define PG11 0x0800
1177	#define PG12 0x1000
1178	#define PG13 0x2000
1179	#define PG14 0x4000
1180	#define PG15 0x8000
1181
1182	/* Port H Masks */
1183	#define PH0 0x0001
1184	#define PH1 0x0002
1185	#define PH2 0x0004
1186	#define PH3 0x0008
1187	#define PH4 0x0010
1188	#define PH5 0x0020
1189	#define PH6 0x0040
1190	#define PH7 0x0080
1191	#define PH8 0x0100
1192	#define PH9 0x0200
1193	#define PH10 0x0400
1194	#define PH11 0x0800
1195	#define PH12 0x1000
1196	#define PH13 0x2000
1197	#define PH14 0x4000
1198	#define PH15 0x8000
1199
1200	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/	1095	/* ******************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ***********************/
1201	/* EBIU_AMGCTL Masks */	1096	/* EBIU_AMGCTL Masks */
1202	#define AMCKEN 0x0001 /* Enable CLKOUT */	1097	#define AMCKEN 0x0001 /* Enable CLKOUT */