aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-bf537/head.S
diff options
context:
space:
mode:
Diffstat (limited to 'arch/blackfin/mach-bf537/head.S')
-rw-r--r--arch/blackfin/mach-bf537/head.S321
1 files changed, 0 insertions, 321 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 6b019eaee0b6..64e0287ab266 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -30,325 +30,11 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
35#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
38#endif 36#endif
39 37
40.extern ___bss_stop
41.extern ___bss_start
42.extern _bf53x_relocate_l1_mem
43
44#define INITIAL_STACK 0xFFB01000
45
46__INIT
47
48ENTRY(__start)
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
51 /* Enable Cycle Counter and Nesting Of Interrupts */
52#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
53 R0 = SYSCFG_SNEN;
54#else
55 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
56#endif
57 SYSCFG = R0;
58 R0 = 0;
59
60 /* Clear Out All the data and pointer Registers */
61 R1 = R0;
62 R2 = R0;
63 R3 = R0;
64 R4 = R0;
65 R5 = R0;
66 R6 = R0;
67
68 P0 = R0;
69 P1 = R0;
70 P2 = R0;
71 P3 = R0;
72 P4 = R0;
73 P5 = R0;
74
75 LC0 = r0;
76 LC1 = r0;
77 L0 = r0;
78 L1 = r0;
79 L2 = r0;
80 L3 = r0;
81
82 /* Clear Out All the DAG Registers */
83 B0 = r0;
84 B1 = r0;
85 B2 = r0;
86 B3 = r0;
87
88 I0 = r0;
89 I1 = r0;
90 I2 = r0;
91 I3 = r0;
92
93 M0 = r0;
94 M1 = r0;
95 M2 = r0;
96 M3 = r0;
97
98 trace_buffer_init(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
102 /* Turn off the icache */
103 p0.l = LO(IMEM_CONTROL);
104 p0.h = HI(IMEM_CONTROL);
105 R1 = [p0];
106 R0 = ~ENICPLB;
107 R0 = R0 & R1;
108
109 /* Anomaly 05000125 */
110#if ANOMALY_05000125
111 CLI R2;
112 SSYNC;
113#endif
114 [p0] = R0;
115 SSYNC;
116#if ANOMALY_05000125
117 STI R2;
118#endif
119
120 /* Turn off the dcache */
121 p0.l = LO(DMEM_CONTROL);
122 p0.h = HI(DMEM_CONTROL);
123 R1 = [p0];
124 R0 = ~ENDCPLB;
125 R0 = R0 & R1;
126
127 /* Anomaly 05000125 */
128#if ANOMALY_05000125
129 CLI R2;
130 SSYNC;
131#endif
132 [p0] = R0;
133 SSYNC;
134#if ANOMALY_05000125
135 STI R2;
136#endif
137
138 /* Initialise General-Purpose I/O Modules on BF537 */
139 /* Rev 0.0 Anomaly 05000212 - PORTx_FER,
140 * PORT_MUX Registers Do Not accept "writes" correctly:
141 */
142 p0.h = hi(BFIN_PORT_MUX);
143 p0.l = lo(BFIN_PORT_MUX);
144#if ANOMALY_05000212
145 R0.L = W[P0]; /* Read */
146 SSYNC;
147#endif
148 R0 = (PGDE_UART | PFTE_UART)(Z);
149#if ANOMALY_05000212
150 W[P0] = R0.L; /* Write */
151 SSYNC;
152#endif
153 W[P0] = R0.L; /* Enable both UARTS */
154 SSYNC;
155
156 p0.h = hi(PORTF_FER);
157 p0.l = lo(PORTF_FER);
158#if ANOMALY_05000212
159 R0.L = W[P0]; /* Read */
160 SSYNC;
161#endif
162 R0 = 0x000F(Z);
163#if ANOMALY_05000212
164 W[P0] = R0.L; /* Write */
165 SSYNC;
166#endif
167 /* Enable peripheral function of PORTF for UART0 and UART1 */
168 W[P0] = R0.L;
169 SSYNC;
170
171#if !defined(CONFIG_BF534)
172 p0.h = hi(EMAC_SYSTAT);
173 p0.l = lo(EMAC_SYSTAT);
174 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
175 R0.l = 0xFFFF;
176 [P0] = R0;
177 SSYNC;
178#endif
179
180 /* Initialise UART - when booting from u-boot, the UART is not disabled
181 * so if we dont initalize here, our serial console gets hosed */
182 p0.h = hi(BFIN_UART_LCR);
183 p0.l = lo(BFIN_UART_LCR);
184 r0 = 0x0(Z);
185 w[p0] = r0.L; /* To enable DLL writes */
186 ssync;
187
188 p0.h = hi(BFIN_UART_DLL);
189 p0.l = lo(BFIN_UART_DLL);
190 r0 = 0x0(Z);
191 w[p0] = r0.L;
192 ssync;
193
194 p0.h = hi(BFIN_UART_DLH);
195 p0.l = lo(BFIN_UART_DLH);
196 r0 = 0x00(Z);
197 w[p0] = r0.L;
198 ssync;
199
200 p0.h = hi(BFIN_UART_GCTL);
201 p0.l = lo(BFIN_UART_GCTL);
202 r0 = 0x0(Z);
203 w[p0] = r0.L; /* To enable UART clock */
204 ssync;
205
206 /* Initialize stack pointer */
207 sp.l = lo(INITIAL_STACK);
208 sp.h = hi(INITIAL_STACK);
209 fp = sp;
210 usp = sp;
211
212#ifdef CONFIG_EARLY_PRINTK
213 SP += -12;
214 call _init_early_exception_vectors;
215 SP += 12;
216#endif
217
218 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
219 call _bf53x_relocate_l1_mem;
220#ifdef CONFIG_BFIN_KERNEL_CLOCK
221 call _start_dma_code;
222#endif
223
224 /* Code for initializing Async memory banks */
225
226 p2.h = hi(EBIU_AMBCTL1);
227 p2.l = lo(EBIU_AMBCTL1);
228 r0.h = hi(AMBCTL1VAL);
229 r0.l = lo(AMBCTL1VAL);
230 [p2] = r0;
231 ssync;
232
233 p2.h = hi(EBIU_AMBCTL0);
234 p2.l = lo(EBIU_AMBCTL0);
235 r0.h = hi(AMBCTL0VAL);
236 r0.l = lo(AMBCTL0VAL);
237 [p2] = r0;
238 ssync;
239
240 p2.h = hi(EBIU_AMGCTL);
241 p2.l = lo(EBIU_AMGCTL);
242 r0 = AMGCTLVAL;
243 w[p2] = r0;
244 ssync;
245
246 /* This section keeps the processor in supervisor mode
247 * during kernel boot. Switches to user mode at end of boot.
248 * See page 3-9 of Hardware Reference manual for documentation.
249 */
250
251 /* EVT15 = _real_start */
252
253 p0.l = lo(EVT15);
254 p0.h = hi(EVT15);
255 p1.l = _real_start;
256 p1.h = _real_start;
257 [p0] = p1;
258 csync;
259
260 p0.l = lo(IMASK);
261 p0.h = hi(IMASK);
262 p1.l = IMASK_IVG15;
263 p1.h = 0x0;
264 [p0] = p1;
265 csync;
266
267 raise 15;
268 p0.l = .LWAIT_HERE;
269 p0.h = .LWAIT_HERE;
270 reti = p0;
271#if ANOMALY_05000281
272 nop; nop; nop;
273#endif
274 rti;
275
276.LWAIT_HERE:
277 jump .LWAIT_HERE;
278ENDPROC(__start)
279
280ENTRY(_real_start)
281 [ -- sp ] = reti;
282 p0.l = lo(WDOG_CTL);
283 p0.h = hi(WDOG_CTL);
284 r0 = 0xAD6(z);
285 w[p0] = r0; /* watchdog off for now */
286 ssync;
287
288 /* Code update for BSS size == 0
289 * Zero out the bss region.
290 */
291
292 p1.l = ___bss_start;
293 p1.h = ___bss_start;
294 p2.l = ___bss_stop;
295 p2.h = ___bss_stop;
296 r0 = 0;
297 p2 -= p1;
298 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
299.L_clear_bss:
300 B[p1++] = r0;
301
302 /* In case there is a NULL pointer reference
303 * Zero out region before stext
304 */
305
306 p1.l = 0x0;
307 p1.h = 0x0;
308 r0.l = __stext;
309 r0.h = __stext;
310 r0 = r0 >> 1;
311 p2 = r0;
312 r0 = 0;
313 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
314.L_clear_zero:
315 W[p1++] = r0;
316
317 /* pass the uboot arguments to the global value command line */
318 R0 = R7;
319 call _cmdline_init;
320
321 p1.l = __rambase;
322 p1.h = __rambase;
323 r0.l = __sdata;
324 r0.h = __sdata;
325 [p1] = r0;
326
327 p1.l = __ramstart;
328 p1.h = __ramstart;
329 p3.l = ___bss_stop;
330 p3.h = ___bss_stop;
331
332 r1 = p3;
333 [p1] = r1;
334
335 /*
336 * load the current thread pointer and stack
337 */
338 r1.l = _init_thread_union;
339 r1.h = _init_thread_union;
340
341 r2.l = 0x2000;
342 r2.h = 0x0000;
343 r1 = r1 + r2;
344 sp = r1;
345 usp = sp;
346 fp = sp;
347 jump.l _start_kernel;
348ENDPROC(_real_start)
349
350__FINIT
351
352.section .l1.text 38.section .l1.text
353#ifdef CONFIG_BFIN_KERNEL_CLOCK 39#ifdef CONFIG_BFIN_KERNEL_CLOCK
354ENTRY(_start_dma_code) 40ENTRY(_start_dma_code)
@@ -452,13 +138,6 @@ ENTRY(_start_dma_code)
452 [P2] = R1; 138 [P2] = R1;
453 SSYNC; 139 SSYNC;
454 140
455 p0.h = hi(SIC_IWR);
456 p0.l = lo(SIC_IWR);
457 r0.l = lo(IWR_ENABLE_ALL);
458 r0.h = hi(IWR_ENABLE_ALL);
459 [p0] = r0;
460 SSYNC;
461
462 RTS; 141 RTS;
463ENDPROC(_start_dma_code) 142ENDPROC(_start_dma_code)
464#endif /* CONFIG_BFIN_KERNEL_CLOCK */ 143#endif /* CONFIG_BFIN_KERNEL_CLOCK */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 01:39:51 -0500