diff options
Diffstat (limited to 'arch/blackfin/mach-bf537/head.S')
-rw-r--r-- | arch/blackfin/mach-bf537/head.S | 46 |
1 files changed, 8 insertions, 38 deletions
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 3014fe8dd155..48cd58a410a0 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S | |||
@@ -37,9 +37,6 @@ | |||
37 | #include <asm/mach/mem_init.h> | 37 | #include <asm/mach/mem_init.h> |
38 | #endif | 38 | #endif |
39 | 39 | ||
40 | .global __rambase | ||
41 | .global __ramstart | ||
42 | .global __ramend | ||
43 | .extern ___bss_stop | 40 | .extern ___bss_stop |
44 | .extern ___bss_start | 41 | .extern ___bss_start |
45 | .extern _bf53x_relocate_l1_mem | 42 | .extern _bf53x_relocate_l1_mem |
@@ -180,40 +177,28 @@ ENTRY(__start) | |||
180 | SSYNC; | 177 | SSYNC; |
181 | #endif | 178 | #endif |
182 | 179 | ||
183 | #ifdef CONFIG_BF537_PORT_H | ||
184 | p0.h = hi(PORTH_FER); | ||
185 | p0.l = lo(PORTH_FER); | ||
186 | R0.L = W[P0]; /* Read */ | ||
187 | SSYNC; | ||
188 | R0 = 0x0000; | ||
189 | W[P0] = R0.L; /* Write */ | ||
190 | SSYNC; | ||
191 | W[P0] = R0.L; /* Disable peripheral function of PORTH */ | ||
192 | SSYNC; | ||
193 | #endif | ||
194 | |||
195 | /* Initialise UART - when booting from u-boot, the UART is not disabled | 180 | /* Initialise UART - when booting from u-boot, the UART is not disabled |
196 | * so if we dont initalize here, our serial console gets hosed */ | 181 | * so if we dont initalize here, our serial console gets hosed */ |
197 | p0.h = hi(UART_LCR); | 182 | p0.h = hi(BFIN_UART_LCR); |
198 | p0.l = lo(UART_LCR); | 183 | p0.l = lo(BFIN_UART_LCR); |
199 | r0 = 0x0(Z); | 184 | r0 = 0x0(Z); |
200 | w[p0] = r0.L; /* To enable DLL writes */ | 185 | w[p0] = r0.L; /* To enable DLL writes */ |
201 | ssync; | 186 | ssync; |
202 | 187 | ||
203 | p0.h = hi(UART_DLL); | 188 | p0.h = hi(BFIN_UART_DLL); |
204 | p0.l = lo(UART_DLL); | 189 | p0.l = lo(BFIN_UART_DLL); |
205 | r0 = 0x0(Z); | 190 | r0 = 0x0(Z); |
206 | w[p0] = r0.L; | 191 | w[p0] = r0.L; |
207 | ssync; | 192 | ssync; |
208 | 193 | ||
209 | p0.h = hi(UART_DLH); | 194 | p0.h = hi(BFIN_UART_DLH); |
210 | p0.l = lo(UART_DLH); | 195 | p0.l = lo(BFIN_UART_DLH); |
211 | r0 = 0x00(Z); | 196 | r0 = 0x00(Z); |
212 | w[p0] = r0.L; | 197 | w[p0] = r0.L; |
213 | ssync; | 198 | ssync; |
214 | 199 | ||
215 | p0.h = hi(UART_GCTL); | 200 | p0.h = hi(BFIN_UART_GCTL); |
216 | p0.l = lo(UART_GCTL); | 201 | p0.l = lo(BFIN_UART_GCTL); |
217 | r0 = 0x0(Z); | 202 | r0 = 0x0(Z); |
218 | w[p0] = r0.L; /* To enable UART clock */ | 203 | w[p0] = r0.L; /* To enable UART clock */ |
219 | ssync; | 204 | ssync; |
@@ -483,18 +468,3 @@ ENTRY(_start_dma_code) | |||
483 | RTS; | 468 | RTS; |
484 | ENDPROC(_start_dma_code) | 469 | ENDPROC(_start_dma_code) |
485 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | 470 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |
486 | |||
487 | .data | ||
488 | |||
489 | /* | ||
490 | * Set up the usable of RAM stuff. Size of RAM is determined then | ||
491 | * an initial stack set up at the end. | ||
492 | */ | ||
493 | |||
494 | .align 4 | ||
495 | __rambase: | ||
496 | .long 0 | ||
497 | __ramstart: | ||
498 | .long 0 | ||
499 | __ramend: | ||
500 | .long 0 | ||