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-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c2
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c14
2 files changed, 0 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 26a04f078a40..4adceb0bdb6d 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -166,7 +166,6 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
166#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) 166#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
167/* SPI ADC chip */ 167/* SPI ADC chip */
168static struct bfin5xx_spi_chip spi_adc_chip_info = { 168static struct bfin5xx_spi_chip spi_adc_chip_info = {
169 .ctl_reg = 0x1000,
170 .enable_dma = 1, /* use dma transfer with this chip*/ 169 .enable_dma = 1, /* use dma transfer with this chip*/
171 .bits_per_word = 16, 170 .bits_per_word = 16,
172}; 171};
@@ -174,7 +173,6 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
174 173
175#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) 174#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
176static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 175static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
177 .ctl_reg = 0x1000,
178 .enable_dma = 0, 176 .enable_dma = 0,
179 .bits_per_word = 16, 177 .bits_per_word = 16,
180}; 178};
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 644be5e5ab6f..48cfbf816b47 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -107,20 +107,6 @@ static struct platform_device dm9000_device2 = {
107 107
108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
109static struct bfin5xx_spi_chip mmc_spi_chip_info = { 109static struct bfin5xx_spi_chip mmc_spi_chip_info = {
110/*
111 * CPOL (Clock Polarity)
112 * 0 - Active high SCK
113 * 1 - Active low SCK
114 * CPHA (Clock Phase) Selects transfer format and operation mode
115 * 0 - SCLK toggles from middle of the first data bit, slave select
116 * pins controlled by hardware.
117 * 1 - SCLK toggles from beginning of first data bit, slave select
118 * pins controller by user software.
119 * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
120 * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
121 * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
122 */
123 .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
124 .enable_dma = 0, /* if 1 - block!!! */ 110 .enable_dma = 0, /* if 1 - block!!! */
125 .bits_per_word = 8, 111 .bits_per_word = 8,
126}; 112};