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-rw-r--r--arch/blackfin/mach-bf533/Kconfig2
-rw-r--r--arch/blackfin/mach-bf533/Makefile2
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/blackstamp.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c39
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c26
-rw-r--r--arch/blackfin/mach-bf533/boards/generic_board.c35
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c58
-rw-r--r--arch/blackfin/mach-bf533/dma.c2
-rw-r--r--arch/blackfin/mach-bf533/head.S137
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h11
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bf533.h4
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_sir.h125
-rw-r--r--arch/blackfin/mach-bf533/include/mach/blackfin.h7
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h177
-rw-r--r--arch/blackfin/mach-bf533/include/mach/dma.h40
-rw-r--r--arch/blackfin/mach-bf533/include/mach/gpio.h34
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h14
-rw-r--r--arch/blackfin/mach-bf533/include/mach/mem_init.h297
-rw-r--r--arch/blackfin/mach-bf533/include/mach/mem_map.h6
21 files changed, 325 insertions, 763 deletions
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig
index 76beb75f12da..14427de7d77f 100644
--- a/arch/blackfin/mach-bf533/Kconfig
+++ b/arch/blackfin/mach-bf533/Kconfig
@@ -59,7 +59,7 @@ config DMA7_UARTTX
59 default 10 59 default 10
60config TIMER0 60config TIMER0
61 int "TIMER0" 61 int "TIMER0"
62 default 11 62 default 8
63config TIMER1 63config TIMER1
64 int "TIMER1" 64 int "TIMER1"
65 default 11 65 default 11
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile
index aa9f2647ee0c..874840f76028 100644
--- a/arch/blackfin/mach-bf533/Makefile
+++ b/arch/blackfin/mach-bf533/Makefile
@@ -2,6 +2,4 @@
2# arch/blackfin/mach-bf533/Makefile 2# arch/blackfin/mach-bf533/Makefile
3# 3#
4 4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o 5obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 72ac3ac8ef76..0c66bf44cfab 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -313,23 +313,33 @@ static struct platform_device bfin_uart_device = {
313#endif 313#endif
314 314
315#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 315#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
316static struct resource bfin_sir_resources[] = {
317#ifdef CONFIG_BFIN_SIR0 316#ifdef CONFIG_BFIN_SIR0
317static struct resource bfin_sir0_resources[] = {
318 { 318 {
319 .start = 0xFFC00400, 319 .start = 0xFFC00400,
320 .end = 0xFFC004FF, 320 .end = 0xFFC004FF,
321 .flags = IORESOURCE_MEM, 321 .flags = IORESOURCE_MEM,
322 }, 322 },
323#endif 323 {
324 .start = IRQ_UART0_RX,
325 .end = IRQ_UART0_RX+1,
326 .flags = IORESOURCE_IRQ,
327 },
328 {
329 .start = CH_UART0_RX,
330 .end = CH_UART0_RX+1,
331 .flags = IORESOURCE_DMA,
332 },
324}; 333};
325 334
326static struct platform_device bfin_sir_device = { 335static struct platform_device bfin_sir0_device = {
327 .name = "bfin_sir", 336 .name = "bfin_sir",
328 .id = 0, 337 .id = 0,
329 .num_resources = ARRAY_SIZE(bfin_sir_resources), 338 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
330 .resource = bfin_sir_resources, 339 .resource = bfin_sir0_resources,
331}; 340};
332#endif 341#endif
342#endif
333 343
334#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 344#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
335 345
@@ -431,7 +441,9 @@ static struct platform_device *h8606_devices[] __initdata = {
431#endif 441#endif
432 442
433#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 443#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
434 &bfin_sir_device, 444#ifdef CONFIG_BFIN_SIR0
445 &bfin_sir0_device,
446#endif
435#endif 447#endif
436 448
437#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE) 449#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index d064ded87719..6ee607c259ac 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -212,23 +212,33 @@ static struct platform_device bfin_uart_device = {
212#endif 212#endif
213 213
214#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 214#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
215static struct resource bfin_sir_resources[] = {
216#ifdef CONFIG_BFIN_SIR0 215#ifdef CONFIG_BFIN_SIR0
216static struct resource bfin_sir0_resources[] = {
217 { 217 {
218 .start = 0xFFC00400, 218 .start = 0xFFC00400,
219 .end = 0xFFC004FF, 219 .end = 0xFFC004FF,
220 .flags = IORESOURCE_MEM, 220 .flags = IORESOURCE_MEM,
221 }, 221 },
222#endif 222 {
223 .start = IRQ_UART0_RX,
224 .end = IRQ_UART0_RX+1,
225 .flags = IORESOURCE_IRQ,
226 },
227 {
228 .start = CH_UART0_RX,
229 .end = CH_UART0_RX+1,
230 .flags = IORESOURCE_DMA,
231 },
223}; 232};
224 233
225static struct platform_device bfin_sir_device = { 234static struct platform_device bfin_sir0_device = {
226 .name = "bfin_sir", 235 .name = "bfin_sir",
227 .id = 0, 236 .id = 0,
228 .num_resources = ARRAY_SIZE(bfin_sir_resources), 237 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
229 .resource = bfin_sir_resources, 238 .resource = bfin_sir0_resources,
230}; 239};
231#endif 240#endif
241#endif
232 242
233#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 243#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
234static struct platform_device bfin_sport0_uart_device = { 244static struct platform_device bfin_sport0_uart_device = {
@@ -353,7 +363,9 @@ static struct platform_device *stamp_devices[] __initdata = {
353#endif 363#endif
354 364
355#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 365#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
356 &bfin_sir_device, 366#ifdef CONFIG_BFIN_SIR0
367 &bfin_sir0_device,
368#endif
357#endif 369#endif
358 370
359#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 371#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index 575843f6d9ef..e7061c7e8c42 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -219,6 +219,19 @@ static struct platform_device smc91x_device = {
219}; 219};
220#endif 220#endif
221 221
222static struct resource bfin_gpios_resources = {
223 .start = 0,
224 .end = MAX_BLACKFIN_GPIOS - 1,
225 .flags = IORESOURCE_IRQ,
226};
227
228static struct platform_device bfin_gpios_device = {
229 .name = "simple-gpio",
230 .id = -1,
231 .num_resources = 1,
232 .resource = &bfin_gpios_resources,
233};
234
222#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 235#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
223static struct resource bfin_uart_resources[] = { 236static struct resource bfin_uart_resources[] = {
224 { 237 {
@@ -237,23 +250,33 @@ static struct platform_device bfin_uart_device = {
237#endif 250#endif
238 251
239#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 252#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
240static struct resource bfin_sir_resources[] = {
241#ifdef CONFIG_BFIN_SIR0 253#ifdef CONFIG_BFIN_SIR0
254static struct resource bfin_sir0_resources[] = {
242 { 255 {
243 .start = 0xFFC00400, 256 .start = 0xFFC00400,
244 .end = 0xFFC004FF, 257 .end = 0xFFC004FF,
245 .flags = IORESOURCE_MEM, 258 .flags = IORESOURCE_MEM,
246 }, 259 },
247#endif 260 {
261 .start = IRQ_UART0_RX,
262 .end = IRQ_UART0_RX+1,
263 .flags = IORESOURCE_IRQ,
264 },
265 {
266 .start = CH_UART0_RX,
267 .end = CH_UART0_RX+1,
268 .flags = IORESOURCE_DMA,
269 },
248}; 270};
249 271
250static struct platform_device bfin_sir_device = { 272static struct platform_device bfin_sir0_device = {
251 .name = "bfin_sir", 273 .name = "bfin_sir",
252 .id = 0, 274 .id = 0,
253 .num_resources = ARRAY_SIZE(bfin_sir_resources), 275 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
254 .resource = bfin_sir_resources, 276 .resource = bfin_sir0_resources,
255}; 277};
256#endif 278#endif
279#endif
257 280
258#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 281#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
259static struct platform_device bfin_sport0_uart_device = { 282static struct platform_device bfin_sport0_uart_device = {
@@ -342,7 +365,9 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
342#endif 365#endif
343 366
344#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 367#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
345 &bfin_sir_device, 368#ifdef CONFIG_BFIN_SIR0
369 &bfin_sir0_device,
370#endif
346#endif 371#endif
347 372
348#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 373#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -365,6 +390,8 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
365#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 390#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
366 &bfin_spi0_device, 391 &bfin_spi0_device,
367#endif 392#endif
393
394 &bfin_gpios_device,
368}; 395};
369 396
370static int __init cm_bf533_init(void) 397static int __init cm_bf533_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index cc2e7eeb1d5a..08cd0969de47 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -46,7 +46,7 @@
46/* 46/*
47 * Name the Board for the /proc/cpuinfo 47 * Name the Board for the /proc/cpuinfo
48 */ 48 */
49const char bfin_board_name[] = "ADDS-BF533-EZKIT"; 49const char bfin_board_name[] = "ADI BF533-EZKIT";
50 50
51#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 51#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
52static struct platform_device rtc_device = { 52static struct platform_device rtc_device = {
@@ -236,23 +236,33 @@ static struct platform_device bfin_uart_device = {
236#endif 236#endif
237 237
238#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 238#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
239static struct resource bfin_sir_resources[] = {
240#ifdef CONFIG_BFIN_SIR0 239#ifdef CONFIG_BFIN_SIR0
240static struct resource bfin_sir0_resources[] = {
241 { 241 {
242 .start = 0xFFC00400, 242 .start = 0xFFC00400,
243 .end = 0xFFC004FF, 243 .end = 0xFFC004FF,
244 .flags = IORESOURCE_MEM, 244 .flags = IORESOURCE_MEM,
245 }, 245 },
246#endif 246 {
247 .start = IRQ_UART0_RX,
248 .end = IRQ_UART0_RX+1,
249 .flags = IORESOURCE_IRQ,
250 },
251 {
252 .start = CH_UART0_RX,
253 .end = CH_UART0_RX+1,
254 .flags = IORESOURCE_DMA,
255 },
247}; 256};
248 257
249static struct platform_device bfin_sir_device = { 258static struct platform_device bfin_sir0_device = {
250 .name = "bfin_sir", 259 .name = "bfin_sir",
251 .id = 0, 260 .id = 0,
252 .num_resources = ARRAY_SIZE(bfin_sir_resources), 261 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
253 .resource = bfin_sir_resources, 262 .resource = bfin_sir0_resources,
254}; 263};
255#endif 264#endif
265#endif
256 266
257#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 267#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
258#include <linux/input.h> 268#include <linux/input.h>
@@ -363,7 +373,9 @@ static struct platform_device *ezkit_devices[] __initdata = {
363#endif 373#endif
364 374
365#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 375#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
366 &bfin_sir_device, 376#ifdef CONFIG_BFIN_SIR0
377 &bfin_sir0_device,
378#endif
367#endif 379#endif
368 380
369#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 381#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c
index 82b1f6a60e3f..986eeec53b1f 100644
--- a/arch/blackfin/mach-bf533/boards/generic_board.c
+++ b/arch/blackfin/mach-bf533/boards/generic_board.c
@@ -72,6 +72,35 @@ static struct platform_device smc91x_device = {
72}; 72};
73#endif 73#endif
74 74
75#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
76#ifdef CONFIG_BFIN_SIR0
77static struct resource bfin_sir0_resources[] = {
78 {
79 .start = 0xFFC00400,
80 .end = 0xFFC004FF,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .start = IRQ_UART0_RX,
85 .end = IRQ_UART0_RX+1,
86 .flags = IORESOURCE_IRQ,
87 },
88 {
89 .start = CH_UART0_RX,
90 .end = CH_UART0_RX+1,
91 .flags = IORESOURCE_DMA,
92 },
93};
94
95static struct platform_device bfin_sir0_device = {
96 .name = "bfin_sir",
97 .id = 0,
98 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
99 .resource = bfin_sir0_resources,
100};
101#endif
102#endif
103
75static struct platform_device *generic_board_devices[] __initdata = { 104static struct platform_device *generic_board_devices[] __initdata = {
76#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 105#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
77 &rtc_device, 106 &rtc_device,
@@ -80,6 +109,12 @@ static struct platform_device *generic_board_devices[] __initdata = {
80#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 109#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
81 &smc91x_device, 110 &smc91x_device,
82#endif 111#endif
112
113#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
114#ifdef CONFIG_BFIN_SIR0
115 &bfin_sir0_device,
116#endif
117#endif
83}; 118};
84 119
85static int __init generic_board_init(void) 120static int __init generic_board_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 5864892de314..e30b1b7d1442 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -197,23 +197,33 @@ static struct platform_device bfin_uart_device = {
197#endif 197#endif
198 198
199#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 199#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
200static struct resource bfin_sir_resources[] = {
201#ifdef CONFIG_BFIN_SIR0 200#ifdef CONFIG_BFIN_SIR0
201static struct resource bfin_sir0_resources[] = {
202 { 202 {
203 .start = 0xFFC00400, 203 .start = 0xFFC00400,
204 .end = 0xFFC004FF, 204 .end = 0xFFC004FF,
205 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
206 }, 206 },
207#endif 207 {
208 .start = IRQ_UART0_RX,
209 .end = IRQ_UART0_RX+1,
210 .flags = IORESOURCE_IRQ,
211 },
212 {
213 .start = CH_UART0_RX,
214 .end = CH_UART0_RX+1,
215 .flags = IORESOURCE_DMA,
216 },
208}; 217};
209 218
210static struct platform_device bfin_sir_device = { 219static struct platform_device bfin_sir0_device = {
211 .name = "bfin_sir", 220 .name = "bfin_sir",
212 .id = 0, 221 .id = 0,
213 .num_resources = ARRAY_SIZE(bfin_sir_resources), 222 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
214 .resource = bfin_sir_resources, 223 .resource = bfin_sir0_resources,
215}; 224};
216#endif 225#endif
226#endif
217 227
218#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 228#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
219static struct resource isp1362_hcd_resources[] = { 229static struct resource isp1362_hcd_resources[] = {
@@ -272,7 +282,9 @@ static struct platform_device *ip0x_devices[] __initdata = {
272#endif 282#endif
273 283
274#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 284#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
275 &bfin_sir_device, 285#ifdef CONFIG_BFIN_SIR0
286 &bfin_sir0_device,
287#endif
276#endif 288#endif
277 289
278#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 290#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 050ffca53530..07f9ad1e189c 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -49,7 +49,7 @@
49/* 49/*
50 * Name the Board for the /proc/cpuinfo 50 * Name the Board for the /proc/cpuinfo
51 */ 51 */
52const char bfin_board_name[] = "ADDS-BF533-STAMP"; 52const char bfin_board_name[] = "ADI BF533-STAMP";
53 53
54#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 54#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
55static struct platform_device rtc_device = { 55static struct platform_device rtc_device = {
@@ -118,7 +118,7 @@ static struct mtd_partition stamp_partitions[] = {
118 .offset = 0, 118 .offset = 0,
119 }, { 119 }, {
120 .name = "linux kernel(nor)", 120 .name = "linux kernel(nor)",
121 .size = 0xE0000, 121 .size = 0x180000,
122 .offset = MTDPART_OFS_APPEND, 122 .offset = MTDPART_OFS_APPEND,
123 }, { 123 }, {
124 .name = "file system(nor)", 124 .name = "file system(nor)",
@@ -169,7 +169,7 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
169 .mask_flags = MTD_CAP_ROM 169 .mask_flags = MTD_CAP_ROM
170 }, { 170 }, {
171 .name = "linux kernel(spi)", 171 .name = "linux kernel(spi)",
172 .size = 0xe0000, 172 .size = 0x180000,
173 .offset = MTDPART_OFS_APPEND, 173 .offset = MTDPART_OFS_APPEND,
174 }, { 174 }, {
175 .name = "file system(spi)", 175 .name = "file system(spi)",
@@ -216,13 +216,6 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
216}; 216};
217#endif 217#endif
218 218
219#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
220static struct bfin5xx_spi_chip spi_mmc_chip_info = {
221 .enable_dma = 1,
222 .bits_per_word = 8,
223};
224#endif
225
226#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 219#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
227static struct bfin5xx_spi_chip spidev_chip_info = { 220static struct bfin5xx_spi_chip spidev_chip_info = {
228 .enable_dma = 0, 221 .enable_dma = 0,
@@ -265,27 +258,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
265 }, 258 },
266#endif 259#endif
267 260
268#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
269 {
270 .modalias = "spi_mmc_dummy",
271 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
272 .bus_num = 0,
273 .chip_select = 0,
274 .platform_data = NULL,
275 .controller_data = &spi_mmc_chip_info,
276 .mode = SPI_MODE_3,
277 },
278 {
279 .modalias = "spi_mmc",
280 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
281 .bus_num = 0,
282 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
283 .platform_data = NULL,
284 .controller_data = &spi_mmc_chip_info,
285 .mode = SPI_MODE_3,
286 },
287#endif
288
289#if defined(CONFIG_PBX) 261#if defined(CONFIG_PBX)
290 { 262 {
291 .modalias = "fxs-spi", 263 .modalias = "fxs-spi",
@@ -373,23 +345,33 @@ static struct platform_device bfin_uart_device = {
373#endif 345#endif
374 346
375#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 347#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
376static struct resource bfin_sir_resources[] = {
377#ifdef CONFIG_BFIN_SIR0 348#ifdef CONFIG_BFIN_SIR0
349static struct resource bfin_sir0_resources[] = {
378 { 350 {
379 .start = 0xFFC00400, 351 .start = 0xFFC00400,
380 .end = 0xFFC004FF, 352 .end = 0xFFC004FF,
381 .flags = IORESOURCE_MEM, 353 .flags = IORESOURCE_MEM,
382 }, 354 },
383#endif 355 {
356 .start = IRQ_UART0_RX,
357 .end = IRQ_UART0_RX+1,
358 .flags = IORESOURCE_IRQ,
359 },
360 {
361 .start = CH_UART0_RX,
362 .end = CH_UART0_RX+1,
363 .flags = IORESOURCE_DMA,
364 },
384}; 365};
385 366
386static struct platform_device bfin_sir_device = { 367static struct platform_device bfin_sir0_device = {
387 .name = "bfin_sir", 368 .name = "bfin_sir",
388 .id = 0, 369 .id = 0,
389 .num_resources = ARRAY_SIZE(bfin_sir_resources), 370 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
390 .resource = bfin_sir_resources, 371 .resource = bfin_sir0_resources,
391}; 372};
392#endif 373#endif
374#endif
393 375
394#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 376#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
395static struct platform_device bfin_sport0_uart_device = { 377static struct platform_device bfin_sport0_uart_device = {
@@ -537,7 +519,9 @@ static struct platform_device *stamp_devices[] __initdata = {
537#endif 519#endif
538 520
539#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) 521#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
540 &bfin_sir_device, 522#ifdef CONFIG_BFIN_SIR0
523 &bfin_sir0_device,
524#endif
541#endif 525#endif
542 526
543#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 527#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
index 28655c1cb7dc..0a6eb8f24d98 100644
--- a/arch/blackfin/mach-bf533/dma.c
+++ b/arch/blackfin/mach-bf533/dma.c
@@ -31,7 +31,7 @@
31#include <asm/blackfin.h> 31#include <asm/blackfin.h>
32#include <asm/dma.h> 32#include <asm/dma.h>
33 33
34struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { 34struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
35 (struct dma_register *) DMA0_NEXT_DESC_PTR, 35 (struct dma_register *) DMA0_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_NEXT_DESC_PTR, 36 (struct dma_register *) DMA1_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_NEXT_DESC_PTR, 37 (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
deleted file mode 100644
index 9fc95aaca439..000000000000
--- a/arch/blackfin/mach-bf533/head.S
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf533/head.S
3 * Based on:
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: bf533 startup file
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/clocks.h>
35#include <mach/mem_init.h>
36#endif
37
38.section .l1.text
39#ifdef CONFIG_BFIN_KERNEL_CLOCK
40ENTRY(_start_dma_code)
41 p0.h = hi(SIC_IWR);
42 p0.l = lo(SIC_IWR);
43 r0.l = 0x1;
44 r0.h = 0x0;
45 [p0] = r0;
46 SSYNC;
47
48 /*
49 * Set PLL_CTL
50 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
51 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
52 * - [7] = output delay (add 200ps of delay to mem signals)
53 * - [6] = input delay (add 200ps of input delay to mem signals)
54 * - [5] = PDWN : 1=All Clocks off
55 * - [3] = STOPCK : 1=Core Clock off
56 * - [1] = PLL_OFF : 1=Disable Power to PLL
57 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
58 * all other bits set to zero
59 */
60
61 p0.h = hi(PLL_LOCKCNT);
62 p0.l = lo(PLL_LOCKCNT);
63 r0 = 0x300(Z);
64 w[p0] = r0.l;
65 ssync;
66
67 P2.H = hi(EBIU_SDGCTL);
68 P2.L = lo(EBIU_SDGCTL);
69 R0 = [P2];
70 BITSET (R0, 24);
71 [P2] = R0;
72 SSYNC;
73
74 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
75 r0 = r0 << 9; /* Shift it over, */
76 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
77 r0 = r1 | r0;
78 r1 = PLL_BYPASS; /* Bypass the PLL? */
79 r1 = r1 << 8; /* Shift it over */
80 r0 = r1 | r0; /* add them all together */
81#ifdef ANOMALY_05000265
82 BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
83#endif
84
85 p0.h = hi(PLL_CTL);
86 p0.l = lo(PLL_CTL); /* Load the address */
87 cli r2; /* Disable interrupts */
88 ssync;
89 w[p0] = r0.l; /* Set the value */
90 idle; /* Wait for the PLL to stablize */
91 sti r2; /* Enable interrupts */
92
93.Lcheck_again:
94 p0.h = hi(PLL_STAT);
95 p0.l = lo(PLL_STAT);
96 R0 = W[P0](Z);
97 CC = BITTST(R0,5);
98 if ! CC jump .Lcheck_again;
99
100 /* Configure SCLK & CCLK Dividers */
101 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
102 p0.h = hi(PLL_DIV);
103 p0.l = lo(PLL_DIV);
104 w[p0] = r0.l;
105 ssync;
106
107 p0.l = lo(EBIU_SDRRC);
108 p0.h = hi(EBIU_SDRRC);
109 r0 = mem_SDRRC;
110 w[p0] = r0.l;
111 ssync;
112
113 P2.H = hi(EBIU_SDGCTL);
114 P2.L = lo(EBIU_SDGCTL);
115 R0 = [P2];
116 BITCLR (R0, 24);
117 p0.h = hi(EBIU_SDSTAT);
118 p0.l = lo(EBIU_SDSTAT);
119 r2.l = w[p0];
120 cc = bittst(r2,3);
121 if !cc jump .Lskip;
122 NOP;
123 BITSET (R0, 23);
124.Lskip:
125 [P2] = R0;
126 SSYNC;
127
128 R0.L = lo(mem_SDGCTL);
129 R0.H = hi(mem_SDGCTL);
130 R1 = [p2];
131 R1 = R1 | R0;
132 [P2] = R1;
133 SSYNC;
134
135 RTS;
136ENDPROC(_start_dma_code)
137#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index f544fc56959a..0d3a03429fb9 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision D, 06/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 10 * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -194,6 +194,12 @@
194#define ANOMALY_05000403 (1) 194#define ANOMALY_05000403 (1)
195/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 195/* Speculative Fetches Can Cause Undesired External FIFO Operations */
196#define ANOMALY_05000416 (1) 196#define ANOMALY_05000416 (1)
197/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
198#define ANOMALY_05000425 (1)
199/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
200#define ANOMALY_05000426 (1)
201/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
202#define ANOMALY_05000443 (1)
197 203
198/* These anomalies have been "phased" out of analog.com anomaly sheets and are 204/* These anomalies have been "phased" out of analog.com anomaly sheets and are
199 * here to show running on older silicon just isn't feasible. 205 * here to show running on older silicon just isn't feasible.
@@ -273,5 +279,8 @@
273#define ANOMALY_05000323 (0) 279#define ANOMALY_05000323 (0)
274#define ANOMALY_05000353 (1) 280#define ANOMALY_05000353 (1)
275#define ANOMALY_05000386 (1) 281#define ANOMALY_05000386 (1)
282#define ANOMALY_05000412 (0)
283#define ANOMALY_05000432 (0)
284#define ANOMALY_05000435 (0)
276 285
277#endif 286#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h
index dfc8c1ad2d7a..cf4427cd3f72 100644
--- a/arch/blackfin/mach-bf533/include/mach/bf533.h
+++ b/arch/blackfin/mach-bf533/include/mach/bf533.h
@@ -145,7 +145,7 @@
145#endif 145#endif
146#ifdef CONFIG_BF532 146#ifdef CONFIG_BF532
147#define CPU "BF532" 147#define CPU "BF532"
148#define CPUID 0x275A 148#define CPUID 0x27a5
149#endif 149#endif
150#ifdef CONFIG_BF531 150#ifdef CONFIG_BF531
151#define CPU "BF531" 151#define CPU "BF531"
@@ -153,7 +153,7 @@
153#endif 153#endif
154 154
155#ifndef CPU 155#ifndef CPU
156#error Unknown CPU type - This kernel doesn't seem to be configured properly 156#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
157#endif 157#endif
158 158
159#endif /* __MACH_BF533_H__ */ 159#endif /* __MACH_BF533_H__ */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_sir.h b/arch/blackfin/mach-bf533/include/mach/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static int bfin_sir_hw_init(void)
114{
115 int ret = -ENODEV;
116#ifdef CONFIG_BFIN_SIR0
117 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
118 if (ret)
119 return ret;
120 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
121 if (ret)
122 return ret;
123#endif
124 return ret;
125}
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
index d80971b4e3aa..045184f81a29 100644
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -44,6 +44,13 @@
44 44
45#define BFIN_UART_NR_PORTS 1 45#define BFIN_UART_NR_PORTS 1
46 46
47#define CH_UART_RX CH_UART0_RX
48#define CH_UART_TX CH_UART0_TX
49
50#define IRQ_UART_ERROR IRQ_UART0_ERROR
51#define IRQ_UART_RX IRQ_UART0_RX
52#define IRQ_UART_TX IRQ_UART0_TX
53
47#define OFFSET_THR 0x00 /* Transmit Holding register */ 54#define OFFSET_THR 0x00 /* Transmit Holding register */
48#define OFFSET_RBR 0x00 /* Receive Buffer register */ 55#define OFFSET_RBR 0x00 /* Receive Buffer register */
49#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 56#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index 3d8978a52c17..bbc3c8386d48 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -39,31 +39,8 @@
39/*include core specific register pointer definitions*/ 39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h> 40#include <asm/cdef_LPBlackfin.h>
41 41
42#include <asm/system.h>
43
44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ 42/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 43#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr = bfin_read32(SIC_IWR);
57 /* Only allow PPL Wakeup) */
58 bfin_write32(SIC_IWR, IWR_ENABLE(0));
59
60 bfin_write16(PLL_CTL, val);
61 SSYNC();
62 asm("IDLE;");
63
64 bfin_write32(SIC_IWR, iwr);
65 local_irq_restore(flags);
66}
67#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 44#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
68#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
69#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -72,27 +49,6 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
72#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 49#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
73#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 50#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
74#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 51#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
75/* Writing to VR_CTL initiates a PLL relock sequence. */
76static __inline__ void bfin_write_VR_CTL(unsigned int val)
77{
78 unsigned long flags, iwr;
79
80 if (val == bfin_read_VR_CTL())
81 return;
82
83 local_irq_save(flags);
84 /* Enable the PLL Wakeup bit in SIC IWR */
85 iwr = bfin_read32(SIC_IWR);
86 /* Only allow PPL Wakeup) */
87 bfin_write32(SIC_IWR, IWR_ENABLE(0));
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR, iwr);
94 local_irq_restore(flags);
95}
96 52
97/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ 53/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
98#define bfin_read_SWRST() bfin_read16(SWRST) 54#define bfin_read_SWRST() bfin_read16(SWRST)
@@ -178,50 +134,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
178#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) 134#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
179#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) 135#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
180 136
181
182#if ANOMALY_05000311
183#define BFIN_WRITE_FIO_FLAG(name) \
184static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\
185{\
186 unsigned long flags;\
187 local_irq_save(flags);\
188 bfin_write16(FIO_FLAG_ ## name,val);\
189 bfin_read_CHIPID();\
190 local_irq_restore(flags);\
191}
192BFIN_WRITE_FIO_FLAG(D)
193BFIN_WRITE_FIO_FLAG(C)
194BFIN_WRITE_FIO_FLAG(S)
195BFIN_WRITE_FIO_FLAG(T)
196
197#define BFIN_READ_FIO_FLAG(name) \
198static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\
199{\
200 unsigned long flags;\
201 unsigned short ret;\
202 local_irq_save(flags);\
203 ret = bfin_read16(FIO_FLAG_ ## name);\
204 bfin_read_CHIPID();\
205 local_irq_restore(flags);\
206 return ret;\
207}
208BFIN_READ_FIO_FLAG(D)
209BFIN_READ_FIO_FLAG(C)
210BFIN_READ_FIO_FLAG(S)
211BFIN_READ_FIO_FLAG(T)
212
213#else
214#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val)
215#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val)
216#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val)
217#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val)
218#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
219#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
220#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
221#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
222#endif
223
224
225/* DMA Controller */ 137/* DMA Controller */
226#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 138#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
227#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) 139#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
@@ -764,4 +676,93 @@ BFIN_READ_FIO_FLAG(T)
764#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 676#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
765#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) 677#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
766 678
679/* These need to be last due to the cdef/linux inter-dependencies */
680#include <asm/irq.h>
681
682#if ANOMALY_05000311
683#define BFIN_WRITE_FIO_FLAG(name) \
684static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
685{ \
686 unsigned long flags; \
687 local_irq_save_hw(flags); \
688 bfin_write16(FIO_FLAG_##name, val); \
689 bfin_read_CHIPID(); \
690 local_irq_restore_hw(flags); \
691}
692BFIN_WRITE_FIO_FLAG(D)
693BFIN_WRITE_FIO_FLAG(C)
694BFIN_WRITE_FIO_FLAG(S)
695BFIN_WRITE_FIO_FLAG(T)
696
697#define BFIN_READ_FIO_FLAG(name) \
698static inline u16 bfin_read_FIO_FLAG_##name(void) \
699{ \
700 unsigned long flags; \
701 u16 ret; \
702 local_irq_save_hw(flags); \
703 ret = bfin_read16(FIO_FLAG_##name); \
704 bfin_read_CHIPID(); \
705 local_irq_restore_hw(flags); \
706 return ret; \
707}
708BFIN_READ_FIO_FLAG(D)
709BFIN_READ_FIO_FLAG(C)
710BFIN_READ_FIO_FLAG(S)
711BFIN_READ_FIO_FLAG(T)
712
713#else
714#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
715#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
716#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
717#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
718#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
719#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
720#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
721#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
722#endif
723
724/* Writing to PLL_CTL initiates a PLL relock sequence. */
725static __inline__ void bfin_write_PLL_CTL(unsigned int val)
726{
727 unsigned long flags, iwr;
728
729 if (val == bfin_read_PLL_CTL())
730 return;
731
732 local_irq_save_hw(flags);
733 /* Enable the PLL Wakeup bit in SIC IWR */
734 iwr = bfin_read32(SIC_IWR);
735 /* Only allow PPL Wakeup) */
736 bfin_write32(SIC_IWR, IWR_ENABLE(0));
737
738 bfin_write16(PLL_CTL, val);
739 SSYNC();
740 asm("IDLE;");
741
742 bfin_write32(SIC_IWR, iwr);
743 local_irq_restore_hw(flags);
744}
745
746/* Writing to VR_CTL initiates a PLL relock sequence. */
747static __inline__ void bfin_write_VR_CTL(unsigned int val)
748{
749 unsigned long flags, iwr;
750
751 if (val == bfin_read_VR_CTL())
752 return;
753
754 local_irq_save_hw(flags);
755 /* Enable the PLL Wakeup bit in SIC IWR */
756 iwr = bfin_read32(SIC_IWR);
757 /* Only allow PPL Wakeup) */
758 bfin_write32(SIC_IWR, IWR_ENABLE(0));
759
760 bfin_write16(VR_CTL, val);
761 SSYNC();
762 asm("IDLE;");
763
764 bfin_write32(SIC_IWR, iwr);
765 local_irq_restore_hw(flags);
766}
767
767#endif /* _CDEF_BF532_H */ 768#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h
index bd9d5e94307d..fb34934c5ba8 100644
--- a/arch/blackfin/mach-bf533/include/mach/dma.h
+++ b/arch/blackfin/mach-bf533/include/mach/dma.h
@@ -1,42 +1,14 @@
1/***************************************************************************** 1/* mach/dma.h - arch-specific DMA defines
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6/*
7 * File: include/asm-blackfin/mach-bf533/dma.h
8 * Based on:
9 * Author:
10 * 2 *
11 * Created: 3 * Copyright 2004-2008 Analog Devices Inc.
12 * Description:
13 * 4 *
14 * Rev: 5 * Licensed under the GPL-2 or later.
15 *
16 * Modified:
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING.
32 * If not, write to the Free Software Foundation,
33 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 */ 6 */
35 7
36#ifndef _MACH_DMA_H_ 8#ifndef _MACH_DMA_H_
37#define _MACH_DMA_H_ 9#define _MACH_DMA_H_
38 10
39#define MAX_BLACKFIN_DMA_CHANNEL 12 11#define MAX_DMA_CHANNELS 12
40 12
41#define CH_PPI 0 13#define CH_PPI 0
42#define CH_SPORT0_RX 1 14#define CH_SPORT0_RX 1
@@ -44,8 +16,8 @@
44#define CH_SPORT1_RX 3 16#define CH_SPORT1_RX 3
45#define CH_SPORT1_TX 4 17#define CH_SPORT1_TX 4
46#define CH_SPI 5 18#define CH_SPI 5
47#define CH_UART_RX 6 19#define CH_UART0_RX 6
48#define CH_UART_TX 7 20#define CH_UART0_TX 7
49#define CH_MEM_STREAM0_DEST 8 /* TX */ 21#define CH_MEM_STREAM0_DEST 8 /* TX */
50#define CH_MEM_STREAM0_SRC 9 /* RX */ 22#define CH_MEM_STREAM0_SRC 9 /* RX */
51#define CH_MEM_STREAM1_DEST 10 /* TX */ 23#define CH_MEM_STREAM1_DEST 10 /* TX */
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
new file mode 100644
index 000000000000..e45c17077aff
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/gpio.h
@@ -0,0 +1,34 @@
1/*
2 * File: arch/blackfin/mach-bf533/include/mach/gpio.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9
10#ifndef _MACH_GPIO_H_
11#define _MACH_GPIO_H_
12
13#define MAX_BLACKFIN_GPIOS 16
14
15#define GPIO_PF0 0
16#define GPIO_PF1 1
17#define GPIO_PF2 2
18#define GPIO_PF3 3
19#define GPIO_PF4 4
20#define GPIO_PF5 5
21#define GPIO_PF6 6
22#define GPIO_PF7 7
23#define GPIO_PF8 8
24#define GPIO_PF9 9
25#define GPIO_PF10 10
26#define GPIO_PF11 11
27#define GPIO_PF12 12
28#define GPIO_PF13 13
29#define GPIO_PF14 14
30#define GPIO_PF15 15
31
32#define PORT_F GPIO_PF0
33
34#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index 5aa38e5da6b7..db1e346cd1aa 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -90,19 +90,19 @@ Core Emulation **
90#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ 90#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
91#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ 91#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
92#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ 92#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
93#define IRQ_UART_ERROR 13 /*UART Error Interrupt */ 93#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
94#define IRQ_RTC 14 /*RTC Interrupt */ 94#define IRQ_RTC 14 /*RTC Interrupt */
95#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ 95#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
96#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ 96#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
97#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ 97#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
98#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ 98#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
99#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ 99#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ 100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
101#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ 101#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
102#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ 102#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
103#define IRQ_TMR0 23 /*Timer 0 */ 103#define IRQ_TIMER0 23 /*Timer 0 */
104#define IRQ_TMR1 24 /*Timer 1 */ 104#define IRQ_TIMER1 24 /*Timer 1 */
105#define IRQ_TMR2 25 /*Timer 2 */ 105#define IRQ_TIMER2 25 /*Timer 2 */
106#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ 106#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
107#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ 107#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
108#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ 108#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_init.h b/arch/blackfin/mach-bf533/include/mach/mem_init.h
deleted file mode 100644
index ed2034bf10ec..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/mem_init.h
+++ /dev/null
@@ -1,297 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
33 CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
34#if (CONFIG_SCLK_HZ > 119402985)
35#define SDRAM_tRP TRP_2
36#define SDRAM_tRP_num 2
37#define SDRAM_tRAS TRAS_7
38#define SDRAM_tRAS_num 7
39#define SDRAM_tRCD TRCD_2
40#define SDRAM_tWR TWR_2
41#endif
42#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
43#define SDRAM_tRP TRP_2
44#define SDRAM_tRP_num 2
45#define SDRAM_tRAS TRAS_6
46#define SDRAM_tRAS_num 6
47#define SDRAM_tRCD TRCD_2
48#define SDRAM_tWR TWR_2
49#endif
50#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
51#define SDRAM_tRP TRP_2
52#define SDRAM_tRP_num 2
53#define SDRAM_tRAS TRAS_5
54#define SDRAM_tRAS_num 5
55#define SDRAM_tRCD TRCD_2
56#define SDRAM_tWR TWR_2
57#endif
58#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
59#define SDRAM_tRP TRP_2
60#define SDRAM_tRP_num 2
61#define SDRAM_tRAS TRAS_4
62#define SDRAM_tRAS_num 4
63#define SDRAM_tRCD TRCD_2
64#define SDRAM_tWR TWR_2
65#endif
66#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
67#define SDRAM_tRP TRP_2
68#define SDRAM_tRP_num 2
69#define SDRAM_tRAS TRAS_3
70#define SDRAM_tRAS_num 3
71#define SDRAM_tRCD TRCD_2
72#define SDRAM_tWR TWR_2
73#endif
74#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
75#define SDRAM_tRP TRP_1
76#define SDRAM_tRP_num 1
77#define SDRAM_tRAS TRAS_4
78#define SDRAM_tRAS_num 3
79#define SDRAM_tRCD TRCD_1
80#define SDRAM_tWR TWR_2
81#endif
82#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
83#define SDRAM_tRP TRP_1
84#define SDRAM_tRP_num 1
85#define SDRAM_tRAS TRAS_3
86#define SDRAM_tRAS_num 3
87#define SDRAM_tRCD TRCD_1
88#define SDRAM_tWR TWR_2
89#endif
90#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
91#define SDRAM_tRP TRP_1
92#define SDRAM_tRP_num 1
93#define SDRAM_tRAS TRAS_2
94#define SDRAM_tRAS_num 2
95#define SDRAM_tRCD TRCD_1
96#define SDRAM_tWR TWR_2
97#endif
98#if (CONFIG_SCLK_HZ <= 29850746)
99#define SDRAM_tRP TRP_1
100#define SDRAM_tRP_num 1
101#define SDRAM_tRAS TRAS_1
102#define SDRAM_tRAS_num 1
103#define SDRAM_tRCD TRCD_1
104#define SDRAM_tWR TWR_2
105#endif
106#endif
107
108#if (CONFIG_MEM_MT48LC16M16A2TG_75)
109 /*SDRAM INFORMATION: */
110#define SDRAM_Tref 64 /* Refresh period in milliseconds */
111#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
112#define SDRAM_CL CL_3
113#endif
114
115#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
116 /*SDRAM INFORMATION: */
117#define SDRAM_Tref 64 /* Refresh period in milliseconds */
118#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
119#define SDRAM_CL CL_3
120#endif
121
122#if (CONFIG_MEM_MT48LC32M16A2TG_75)
123 /*SDRAM INFORMATION: */
124#define SDRAM_Tref 64 /* Refresh period in milliseconds */
125#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
126#define SDRAM_CL CL_3
127#endif
128
129#if (CONFIG_MEM_GENERIC_BOARD)
130 /*SDRAM INFORMATION: Modify this for your board */
131#define SDRAM_Tref 64 /* Refresh period in milliseconds */
132#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
133#define SDRAM_CL CL_3
134#endif
135
136/* Equation from section 17 (p17-46) of BF533 HRM */
137#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
138
139/* Enable SCLK Out */
140#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
141
142#if defined CONFIG_CLKIN_HALF
143#define CLKIN_HALF 1
144#else
145#define CLKIN_HALF 0
146#endif
147
148#if defined CONFIG_PLL_BYPASS
149#define PLL_BYPASS 1
150#else
151#define PLL_BYPASS 0
152#endif
153
154/***************************************Currently Not Being Used *********************************/
155#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
156#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
158#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
159#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
160
161#if (flash_EBIU_AMBCTL_TT > 3)
162#define flash_EBIU_AMBCTL0_TT B0TT_4
163#endif
164#if (flash_EBIU_AMBCTL_TT == 3)
165#define flash_EBIU_AMBCTL0_TT B0TT_3
166#endif
167#if (flash_EBIU_AMBCTL_TT == 2)
168#define flash_EBIU_AMBCTL0_TT B0TT_2
169#endif
170#if (flash_EBIU_AMBCTL_TT < 2)
171#define flash_EBIU_AMBCTL0_TT B0TT_1
172#endif
173
174#if (flash_EBIU_AMBCTL_ST > 3)
175#define flash_EBIU_AMBCTL0_ST B0ST_4
176#endif
177#if (flash_EBIU_AMBCTL_ST == 3)
178#define flash_EBIU_AMBCTL0_ST B0ST_3
179#endif
180#if (flash_EBIU_AMBCTL_ST == 2)
181#define flash_EBIU_AMBCTL0_ST B0ST_2
182#endif
183#if (flash_EBIU_AMBCTL_ST < 2)
184#define flash_EBIU_AMBCTL0_ST B0ST_1
185#endif
186
187#if (flash_EBIU_AMBCTL_HT > 2)
188#define flash_EBIU_AMBCTL0_HT B0HT_3
189#endif
190#if (flash_EBIU_AMBCTL_HT == 2)
191#define flash_EBIU_AMBCTL0_HT B0HT_2
192#endif
193#if (flash_EBIU_AMBCTL_HT == 1)
194#define flash_EBIU_AMBCTL0_HT B0HT_1
195#endif
196#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
197#define flash_EBIU_AMBCTL0_HT B0HT_0
198#endif
199#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
200#define flash_EBIU_AMBCTL0_HT B0HT_1
201#endif
202
203#if (flash_EBIU_AMBCTL_WAT > 14)
204#define flash_EBIU_AMBCTL0_WAT B0WAT_15
205#endif
206#if (flash_EBIU_AMBCTL_WAT == 14)
207#define flash_EBIU_AMBCTL0_WAT B0WAT_14
208#endif
209#if (flash_EBIU_AMBCTL_WAT == 13)
210#define flash_EBIU_AMBCTL0_WAT B0WAT_13
211#endif
212#if (flash_EBIU_AMBCTL_WAT == 12)
213#define flash_EBIU_AMBCTL0_WAT B0WAT_12
214#endif
215#if (flash_EBIU_AMBCTL_WAT == 11)
216#define flash_EBIU_AMBCTL0_WAT B0WAT_11
217#endif
218#if (flash_EBIU_AMBCTL_WAT == 10)
219#define flash_EBIU_AMBCTL0_WAT B0WAT_10
220#endif
221#if (flash_EBIU_AMBCTL_WAT == 9)
222#define flash_EBIU_AMBCTL0_WAT B0WAT_9
223#endif
224#if (flash_EBIU_AMBCTL_WAT == 8)
225#define flash_EBIU_AMBCTL0_WAT B0WAT_8
226#endif
227#if (flash_EBIU_AMBCTL_WAT == 7)
228#define flash_EBIU_AMBCTL0_WAT B0WAT_7
229#endif
230#if (flash_EBIU_AMBCTL_WAT == 6)
231#define flash_EBIU_AMBCTL0_WAT B0WAT_6
232#endif
233#if (flash_EBIU_AMBCTL_WAT == 5)
234#define flash_EBIU_AMBCTL0_WAT B0WAT_5
235#endif
236#if (flash_EBIU_AMBCTL_WAT == 4)
237#define flash_EBIU_AMBCTL0_WAT B0WAT_4
238#endif
239#if (flash_EBIU_AMBCTL_WAT == 3)
240#define flash_EBIU_AMBCTL0_WAT B0WAT_3
241#endif
242#if (flash_EBIU_AMBCTL_WAT == 2)
243#define flash_EBIU_AMBCTL0_WAT B0WAT_2
244#endif
245#if (flash_EBIU_AMBCTL_WAT == 1)
246#define flash_EBIU_AMBCTL0_WAT B0WAT_1
247#endif
248
249#if (flash_EBIU_AMBCTL_RAT > 14)
250#define flash_EBIU_AMBCTL0_RAT B0RAT_15
251#endif
252#if (flash_EBIU_AMBCTL_RAT == 14)
253#define flash_EBIU_AMBCTL0_RAT B0RAT_14
254#endif
255#if (flash_EBIU_AMBCTL_RAT == 13)
256#define flash_EBIU_AMBCTL0_RAT B0RAT_13
257#endif
258#if (flash_EBIU_AMBCTL_RAT == 12)
259#define flash_EBIU_AMBCTL0_RAT B0RAT_12
260#endif
261#if (flash_EBIU_AMBCTL_RAT == 11)
262#define flash_EBIU_AMBCTL0_RAT B0RAT_11
263#endif
264#if (flash_EBIU_AMBCTL_RAT == 10)
265#define flash_EBIU_AMBCTL0_RAT B0RAT_10
266#endif
267#if (flash_EBIU_AMBCTL_RAT == 9)
268#define flash_EBIU_AMBCTL0_RAT B0RAT_9
269#endif
270#if (flash_EBIU_AMBCTL_RAT == 8)
271#define flash_EBIU_AMBCTL0_RAT B0RAT_8
272#endif
273#if (flash_EBIU_AMBCTL_RAT == 7)
274#define flash_EBIU_AMBCTL0_RAT B0RAT_7
275#endif
276#if (flash_EBIU_AMBCTL_RAT == 6)
277#define flash_EBIU_AMBCTL0_RAT B0RAT_6
278#endif
279#if (flash_EBIU_AMBCTL_RAT == 5)
280#define flash_EBIU_AMBCTL0_RAT B0RAT_5
281#endif
282#if (flash_EBIU_AMBCTL_RAT == 4)
283#define flash_EBIU_AMBCTL0_RAT B0RAT_4
284#endif
285#if (flash_EBIU_AMBCTL_RAT == 3)
286#define flash_EBIU_AMBCTL0_RAT B0RAT_3
287#endif
288#if (flash_EBIU_AMBCTL_RAT == 2)
289#define flash_EBIU_AMBCTL0_RAT B0RAT_2
290#endif
291#if (flash_EBIU_AMBCTL_RAT == 1)
292#define flash_EBIU_AMBCTL0_RAT B0RAT_1
293#endif
294
295#define flash_EBIU_AMBCTL0 \
296 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
297 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h
index 581fc6eea789..fc33b7cb9937 100644
--- a/arch/blackfin/mach-bf533/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h
@@ -168,4 +168,10 @@
168#define L1_SCRATCH_START 0xFFB00000 168#define L1_SCRATCH_START 0xFFB00000
169#define L1_SCRATCH_LENGTH 0x1000 169#define L1_SCRATCH_LENGTH 0x1000
170 170
171#define GET_PDA_SAFE(preg) \
172 preg.l = _cpu_pda; \
173 preg.h = _cpu_pda;
174
175#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
176
171#endif /* _MEM_MAP_533_H_ */ 177#endif /* _MEM_MAP_533_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 01:34:46 -0500