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-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c81
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c91
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c119
-rw-r--r--arch/blackfin/mach-bf533/head.S344
4 files changed, 281 insertions, 354 deletions
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index 4545f363e641..a57b52d207cd 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -34,7 +34,9 @@
34#include <linux/spi/spi.h> 34#include <linux/spi/spi.h>
35#include <linux/spi/flash.h> 35#include <linux/spi/flash.h>
36#include <linux/usb_isp1362.h> 36#include <linux/usb_isp1362.h>
37#include <linux/pata_platform.h>
37#include <linux/irq.h> 38#include <linux/irq.h>
39#include <asm/dma.h>
38#include <asm/bfin5xx_spi.h> 40#include <asm/bfin5xx_spi.h>
39 41
40/* 42/*
@@ -93,7 +95,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
93 /* the modalias must be the same as spi device driver name */ 95 /* the modalias must be the same as spi device driver name */
94 .modalias = "m25p80", /* Name of spi_driver for this device */ 96 .modalias = "m25p80", /* Name of spi_driver for this device */
95 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 97 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
96 .bus_num = 1, /* Framework bus number */ 98 .bus_num = 0, /* Framework bus number */
97 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ 99 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
98 .platform_data = &bfin_spi_flash_data, 100 .platform_data = &bfin_spi_flash_data,
99 .controller_data = &spi_flash_chip_info, 101 .controller_data = &spi_flash_chip_info,
@@ -101,7 +103,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
101 }, { 103 }, {
102 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ 104 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
103 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ 105 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
104 .bus_num = 1, /* Framework bus number */ 106 .bus_num = 0, /* Framework bus number */
105 .chip_select = 2, /* Framework chip select. */ 107 .chip_select = 2, /* Framework chip select. */
106 .platform_data = NULL, /* No spi_driver specific config */ 108 .platform_data = NULL, /* No spi_driver specific config */
107 .controller_data = &spi_adc_chip_info, 109 .controller_data = &spi_adc_chip_info,
@@ -110,24 +112,40 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
110 { 112 {
111 .modalias = "ad1836-spi", 113 .modalias = "ad1836-spi",
112 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 114 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
113 .bus_num = 1, 115 .bus_num = 0,
114 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 116 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
115 .controller_data = &ad1836_spi_chip_info, 117 .controller_data = &ad1836_spi_chip_info,
116 }, 118 },
117#endif 119#endif
118}; 120};
119 121
122/* SPI (0) */
123static struct resource bfin_spi0_resource[] = {
124 [0] = {
125 .start = SPI0_REGBASE,
126 .end = SPI0_REGBASE + 0xFF,
127 .flags = IORESOURCE_MEM,
128 },
129 [1] = {
130 .start = CH_SPI,
131 .end = CH_SPI,
132 .flags = IORESOURCE_IRQ,
133 }
134};
135
120/* SPI controller data */ 136/* SPI controller data */
121static struct bfin5xx_spi_master spi_bfin_master_info = { 137static struct bfin5xx_spi_master bfin_spi0_info = {
122 .num_chipselect = 8, 138 .num_chipselect = 8,
123 .enable_dma = 1, /* master has the ability to do dma transfer */ 139 .enable_dma = 1, /* master has the ability to do dma transfer */
124}; 140};
125 141
126static struct platform_device spi_bfin_master_device = { 142static struct platform_device bfin_spi0_device = {
127 .name = "bfin-spi-master", 143 .name = "bfin-spi",
128 .id = 1, /* Bus number */ 144 .id = 0, /* Bus number */
145 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
146 .resource = bfin_spi0_resource,
129 .dev = { 147 .dev = {
130 .platform_data = &spi_bfin_master_info, /* Passed to driver */ 148 .platform_data = &bfin_spi0_info, /* Passed to driver */
131 }, 149 },
132}; 150};
133#endif /* spi master and devices */ 151#endif /* spi master and devices */
@@ -227,6 +245,43 @@ static struct platform_device isp1362_hcd_device = {
227}; 245};
228#endif 246#endif
229 247
248#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
249#define PATA_INT 38
250
251static struct pata_platform_info bfin_pata_platform_data = {
252 .ioport_shift = 2,
253 .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
254};
255
256static struct resource bfin_pata_resources[] = {
257 {
258 .start = 0x2030C000,
259 .end = 0x2030C01F,
260 .flags = IORESOURCE_MEM,
261 },
262 {
263 .start = 0x2030D018,
264 .end = 0x2030D01B,
265 .flags = IORESOURCE_MEM,
266 },
267 {
268 .start = PATA_INT,
269 .end = PATA_INT,
270 .flags = IORESOURCE_IRQ,
271 },
272};
273
274static struct platform_device bfin_pata_device = {
275 .name = "pata_platform",
276 .id = -1,
277 .num_resources = ARRAY_SIZE(bfin_pata_resources),
278 .resource = bfin_pata_resources,
279 .dev = {
280 .platform_data = &bfin_pata_platform_data,
281 }
282};
283#endif
284
230static struct platform_device *cm_bf533_devices[] __initdata = { 285static struct platform_device *cm_bf533_devices[] __initdata = {
231#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 286#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
232 &bfin_uart_device, 287 &bfin_uart_device,
@@ -250,7 +305,11 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
250#endif 305#endif
251 306
252#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 307#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
253 &spi_bfin_master_device, 308 &bfin_spi0_device,
309#endif
310
311#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
312 &bfin_pata_device,
254#endif 313#endif
255}; 314};
256 315
@@ -261,6 +320,10 @@ static int __init cm_bf533_init(void)
261#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 320#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
262 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 321 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
263#endif 322#endif
323
324#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
325 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
326#endif
264 return 0; 327 return 0;
265} 328}
266 329
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 0000b8f1239c..5c1e35d3c012 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -35,7 +35,9 @@
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h> 37#include <linux/usb_isp1362.h>
38#include <linux/pata_platform.h>
38#include <linux/irq.h> 39#include <linux/irq.h>
40#include <asm/dma.h>
39#include <asm/bfin5xx_spi.h> 41#include <asm/bfin5xx_spi.h>
40 42
41/* 43/*
@@ -50,6 +52,12 @@ static struct platform_device rtc_device = {
50}; 52};
51#endif 53#endif
52 54
55#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
56static struct platform_device bfin_fb_adv7393_device = {
57 .name = "bfin-adv7393",
58};
59#endif
60
53/* 61/*
54 * USB-LAN EzExtender board 62 * USB-LAN EzExtender board
55 * Driver needs to know address, irq and flag pin. 63 * Driver needs to know address, irq and flag pin.
@@ -131,7 +139,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
131 /* the modalias must be the same as spi device driver name */ 139 /* the modalias must be the same as spi device driver name */
132 .modalias = "m25p80", /* Name of spi_driver for this device */ 140 .modalias = "m25p80", /* Name of spi_driver for this device */
133 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 141 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
134 .bus_num = 1, /* Framework bus number */ 142 .bus_num = 0, /* Framework bus number */
135 .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ 143 .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
136 .platform_data = &bfin_spi_flash_data, 144 .platform_data = &bfin_spi_flash_data,
137 .controller_data = &spi_flash_chip_info, 145 .controller_data = &spi_flash_chip_info,
@@ -143,7 +151,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
143 { 151 {
144 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ 152 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
145 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ 153 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
146 .bus_num = 1, /* Framework bus number */ 154 .bus_num = 0, /* Framework bus number */
147 .chip_select = 1, /* Framework chip select. */ 155 .chip_select = 1, /* Framework chip select. */
148 .platform_data = NULL, /* No spi_driver specific config */ 156 .platform_data = NULL, /* No spi_driver specific config */
149 .controller_data = &spi_adc_chip_info, 157 .controller_data = &spi_adc_chip_info,
@@ -154,24 +162,40 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
154 { 162 {
155 .modalias = "ad1836-spi", 163 .modalias = "ad1836-spi",
156 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 164 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
157 .bus_num = 1, 165 .bus_num = 0,
158 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 166 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
159 .controller_data = &ad1836_spi_chip_info, 167 .controller_data = &ad1836_spi_chip_info,
160 }, 168 },
161#endif 169#endif
162}; 170};
163 171
172/* SPI (0) */
173static struct resource bfin_spi0_resource[] = {
174 [0] = {
175 .start = SPI0_REGBASE,
176 .end = SPI0_REGBASE + 0xFF,
177 .flags = IORESOURCE_MEM,
178 },
179 [1] = {
180 .start = CH_SPI,
181 .end = CH_SPI,
182 .flags = IORESOURCE_IRQ,
183 }
184};
185
164/* SPI controller data */ 186/* SPI controller data */
165static struct bfin5xx_spi_master spi_bfin_master_info = { 187static struct bfin5xx_spi_master bfin_spi0_info = {
166 .num_chipselect = 8, 188 .num_chipselect = 8,
167 .enable_dma = 1, /* master has the ability to do dma transfer */ 189 .enable_dma = 1, /* master has the ability to do dma transfer */
168}; 190};
169 191
170static struct platform_device spi_bfin_master_device = { 192static struct platform_device bfin_spi0_device = {
171 .name = "bfin-spi-master", 193 .name = "bfin-spi",
172 .id = 1, /* Bus number */ 194 .id = 0, /* Bus number */
195 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
196 .resource = bfin_spi0_resource,
173 .dev = { 197 .dev = {
174 .platform_data = &spi_bfin_master_info, /* Passed to driver */ 198 .platform_data = &bfin_spi0_info, /* Passed to driver */
175 }, 199 },
176}; 200};
177#endif /* spi master and devices */ 201#endif /* spi master and devices */
@@ -193,13 +217,54 @@ static struct platform_device bfin_uart_device = {
193}; 217};
194#endif 218#endif
195 219
220#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
221#define PATA_INT 55
222
223static struct pata_platform_info bfin_pata_platform_data = {
224 .ioport_shift = 1,
225 .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
226};
227
228static struct resource bfin_pata_resources[] = {
229 {
230 .start = 0x20314020,
231 .end = 0x2031403F,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .start = 0x2031401C,
236 .end = 0x2031401F,
237 .flags = IORESOURCE_MEM,
238 },
239 {
240 .start = PATA_INT,
241 .end = PATA_INT,
242 .flags = IORESOURCE_IRQ,
243 },
244};
245
246static struct platform_device bfin_pata_device = {
247 .name = "pata_platform",
248 .id = -1,
249 .num_resources = ARRAY_SIZE(bfin_pata_resources),
250 .resource = bfin_pata_resources,
251 .dev = {
252 .platform_data = &bfin_pata_platform_data,
253 }
254};
255#endif
256
196static struct platform_device *ezkit_devices[] __initdata = { 257static struct platform_device *ezkit_devices[] __initdata = {
197#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 258#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
198 &smc91x_device, 259 &smc91x_device,
199#endif 260#endif
200 261
201#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 262#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
202 &spi_bfin_master_device, 263 &bfin_spi0_device,
264#endif
265
266#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
267 &bfin_fb_adv7393_device,
203#endif 268#endif
204 269
205#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 270#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
@@ -209,6 +274,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
209#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 274#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
210 &bfin_uart_device, 275 &bfin_uart_device,
211#endif 276#endif
277
278#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
279 &bfin_pata_device,
280#endif
212}; 281};
213 282
214static int __init ezkit_init(void) 283static int __init ezkit_init(void)
@@ -218,6 +287,10 @@ static int __init ezkit_init(void)
218#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 287#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
219 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 288 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
220#endif 289#endif
290
291#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
292 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
293#endif
221 return 0; 294 return 0;
222} 295}
223 296
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index a9143c4cbdcd..8975e06ea158 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -37,8 +37,11 @@
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h> 38#include <linux/usb_isp1362.h>
39#endif 39#endif
40#include <linux/pata_platform.h>
40#include <linux/irq.h> 41#include <linux/irq.h>
42#include <asm/dma.h>
41#include <asm/bfin5xx_spi.h> 43#include <asm/bfin5xx_spi.h>
44#include <asm/reboot.h>
42 45
43/* 46/*
44 * Name the Board for the /proc/cpuinfo 47 * Name the Board for the /proc/cpuinfo
@@ -77,6 +80,12 @@ static struct platform_device smc91x_device = {
77}; 80};
78#endif 81#endif
79 82
83#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
84static struct platform_device bfin_fb_adv7393_device = {
85 .name = "bfin-adv7393",
86};
87#endif
88
80#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) 89#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
81static struct resource net2272_bfin_resources[] = { 90static struct resource net2272_bfin_resources[] = {
82 { 91 {
@@ -177,7 +186,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
177 /* the modalias must be the same as spi device driver name */ 186 /* the modalias must be the same as spi device driver name */
178 .modalias = "m25p80", /* Name of spi_driver for this device */ 187 .modalias = "m25p80", /* Name of spi_driver for this device */
179 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 188 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
180 .bus_num = 1, /* Framework bus number */ 189 .bus_num = 0, /* Framework bus number */
181 .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ 190 .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
182 .platform_data = &bfin_spi_flash_data, 191 .platform_data = &bfin_spi_flash_data,
183 .controller_data = &spi_flash_chip_info, 192 .controller_data = &spi_flash_chip_info,
@@ -189,7 +198,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
189 { 198 {
190 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ 199 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
191 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ 200 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
192 .bus_num = 1, /* Framework bus number */ 201 .bus_num = 0, /* Framework bus number */
193 .chip_select = 1, /* Framework chip select. */ 202 .chip_select = 1, /* Framework chip select. */
194 .platform_data = NULL, /* No spi_driver specific config */ 203 .platform_data = NULL, /* No spi_driver specific config */
195 .controller_data = &spi_adc_chip_info, 204 .controller_data = &spi_adc_chip_info,
@@ -200,7 +209,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
200 { 209 {
201 .modalias = "ad1836-spi", 210 .modalias = "ad1836-spi",
202 .max_speed_hz = 31250000, /* max spi clock (SCK) speed in HZ */ 211 .max_speed_hz = 31250000, /* max spi clock (SCK) speed in HZ */
203 .bus_num = 1, 212 .bus_num = 0,
204 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 213 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
205 .controller_data = &ad1836_spi_chip_info, 214 .controller_data = &ad1836_spi_chip_info,
206 }, 215 },
@@ -210,7 +219,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
210 { 219 {
211 .modalias = "spi_mmc_dummy", 220 .modalias = "spi_mmc_dummy",
212 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 221 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
213 .bus_num = 1, 222 .bus_num = 0,
214 .chip_select = 0, 223 .chip_select = 0,
215 .platform_data = NULL, 224 .platform_data = NULL,
216 .controller_data = &spi_mmc_chip_info, 225 .controller_data = &spi_mmc_chip_info,
@@ -219,7 +228,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
219 { 228 {
220 .modalias = "spi_mmc", 229 .modalias = "spi_mmc",
221 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 230 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
222 .bus_num = 1, 231 .bus_num = 0,
223 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 232 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
224 .platform_data = NULL, 233 .platform_data = NULL,
225 .controller_data = &spi_mmc_chip_info, 234 .controller_data = &spi_mmc_chip_info,
@@ -231,16 +240,16 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
231 { 240 {
232 .modalias = "fxs-spi", 241 .modalias = "fxs-spi",
233 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 242 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
234 .bus_num = 1, 243 .bus_num = 0,
235 .chip_select = 3, 244 .chip_select = 8 - CONFIG_J11_JUMPER,
236 .controller_data = &spi_si3xxx_chip_info, 245 .controller_data = &spi_si3xxx_chip_info,
237 .mode = SPI_MODE_3, 246 .mode = SPI_MODE_3,
238 }, 247 },
239 { 248 {
240 .modalias = "fxo-spi", 249 .modalias = "fxo-spi",
241 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 250 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
242 .bus_num = 1, 251 .bus_num = 0,
243 .chip_select = 2, 252 .chip_select = 8 - CONFIG_J19_JUMPER,
244 .controller_data = &spi_si3xxx_chip_info, 253 .controller_data = &spi_si3xxx_chip_info,
245 .mode = SPI_MODE_3, 254 .mode = SPI_MODE_3,
246 }, 255 },
@@ -250,7 +259,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
250 { 259 {
251 .modalias = "ad5304_spi", 260 .modalias = "ad5304_spi",
252 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ 261 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
253 .bus_num = 1, 262 .bus_num = 0,
254 .chip_select = 2, 263 .chip_select = 2,
255 .platform_data = NULL, 264 .platform_data = NULL,
256 .controller_data = &ad5304_chip_info, 265 .controller_data = &ad5304_chip_info,
@@ -259,17 +268,33 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
259#endif 268#endif
260}; 269};
261 270
271/* SPI (0) */
272static struct resource bfin_spi0_resource[] = {
273 [0] = {
274 .start = SPI0_REGBASE,
275 .end = SPI0_REGBASE + 0xFF,
276 .flags = IORESOURCE_MEM,
277 },
278 [1] = {
279 .start = CH_SPI,
280 .end = CH_SPI,
281 .flags = IORESOURCE_IRQ,
282 }
283};
284
262/* SPI controller data */ 285/* SPI controller data */
263static struct bfin5xx_spi_master spi_bfin_master_info = { 286static struct bfin5xx_spi_master bfin_spi0_info = {
264 .num_chipselect = 8, 287 .num_chipselect = 8,
265 .enable_dma = 1, /* master has the ability to do dma transfer */ 288 .enable_dma = 1, /* master has the ability to do dma transfer */
266}; 289};
267 290
268static struct platform_device spi_bfin_master_device = { 291static struct platform_device bfin_spi0_device = {
269 .name = "bfin-spi-master", 292 .name = "bfin-spi",
270 .id = 1, /* Bus number */ 293 .id = 0, /* Bus number */
294 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
295 .resource = bfin_spi0_resource,
271 .dev = { 296 .dev = {
272 .platform_data = &spi_bfin_master_info, /* Passed to driver */ 297 .platform_data = &bfin_spi0_info, /* Passed to driver */
273 }, 298 },
274}; 299};
275#endif /* spi master and devices */ 300#endif /* spi master and devices */
@@ -309,6 +334,43 @@ static struct platform_device bfin_sport1_uart_device = {
309}; 334};
310#endif 335#endif
311 336
337#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
338#define PATA_INT 55
339
340static struct pata_platform_info bfin_pata_platform_data = {
341 .ioport_shift = 1,
342 .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
343};
344
345static struct resource bfin_pata_resources[] = {
346 {
347 .start = 0x20314020,
348 .end = 0x2031403F,
349 .flags = IORESOURCE_MEM,
350 },
351 {
352 .start = 0x2031401C,
353 .end = 0x2031401F,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .start = PATA_INT,
358 .end = PATA_INT,
359 .flags = IORESOURCE_IRQ,
360 },
361};
362
363static struct platform_device bfin_pata_device = {
364 .name = "pata_platform",
365 .id = -1,
366 .num_resources = ARRAY_SIZE(bfin_pata_resources),
367 .resource = bfin_pata_resources,
368 .dev = {
369 .platform_data = &bfin_pata_platform_data,
370 }
371};
372#endif
373
312static struct platform_device *stamp_devices[] __initdata = { 374static struct platform_device *stamp_devices[] __initdata = {
313#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 375#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
314 &rtc_device, 376 &rtc_device,
@@ -318,12 +380,16 @@ static struct platform_device *stamp_devices[] __initdata = {
318 &smc91x_device, 380 &smc91x_device,
319#endif 381#endif
320 382
383#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
384 &bfin_fb_adv7393_device,
385#endif
386
321#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) 387#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
322 &net2272_bfin_device, 388 &net2272_bfin_device,
323#endif 389#endif
324 390
325#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 391#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
326 &spi_bfin_master_device, 392 &bfin_spi0_device,
327#endif 393#endif
328 394
329#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 395#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
@@ -334,6 +400,10 @@ static struct platform_device *stamp_devices[] __initdata = {
334 &bfin_sport0_uart_device, 400 &bfin_sport0_uart_device,
335 &bfin_sport1_uart_device, 401 &bfin_sport1_uart_device,
336#endif 402#endif
403
404#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
405 &bfin_pata_device,
406#endif
337}; 407};
338 408
339static int __init stamp_init(void) 409static int __init stamp_init(void)
@@ -355,8 +425,23 @@ static int __init stamp_init(void)
355#endif 425#endif
356 426
357#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 427#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
358 return spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 428 spi_register_board_info(bfin_spi_board_info,
429 ARRAY_SIZE(bfin_spi_board_info));
430#endif
431#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
432 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
359#endif 433#endif
434 return 0;
360} 435}
361 436
362arch_initcall(stamp_init); 437arch_initcall(stamp_init);
438
439void native_machine_restart(char *cmd)
440{
441#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
442# define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN)
443 bfin_write_FIO_INEN(~BIT_TO_SET);
444 bfin_write_FIO_DIR(BIT_TO_SET);
445 bfin_write_FIO_FLAG_C(BIT_TO_SET);
446#endif
447}
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7dd0e9c3a936..1ded945a6fa0 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -32,11 +32,9 @@
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h> 33#include <asm/trace.h>
34#if CONFIG_BFIN_KERNEL_CLOCK 34#if CONFIG_BFIN_KERNEL_CLOCK
35#include <asm/mach-common/clocks.h>
35#include <asm/mach/mem_init.h> 36#include <asm/mach/mem_init.h>
36#endif 37#endif
37#if CONFIG_DEBUG_KERNEL_START
38#include <asm/mach-common/def_LPBlackfin.h>
39#endif
40 38
41.global __rambase 39.global __rambase
42.global __ramstart 40.global __ramstart
@@ -52,10 +50,12 @@ __INIT
52ENTRY(__start) 50ENTRY(__start)
53 /* R0: argument of command line string, passed from uboot, save it */ 51 /* R0: argument of command line string, passed from uboot, save it */
54 R7 = R0; 52 R7 = R0;
55 /* Set the SYSCFG register: 53 /* Enable Cycle Counter and Nesting Of Interrupts */
56 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit) 54#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
57 */ 55 R0 = SYSCFG_SNEN;
58 R0 = 0x36; 56#else
57 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
58#endif
59 SYSCFG = R0; 59 SYSCFG = R0;
60 R0 = 0; 60 R0 = 0;
61 61
@@ -97,40 +97,10 @@ ENTRY(__start)
97 M2 = r0; 97 M2 = r0;
98 M3 = r0; 98 M3 = r0;
99 99
100 trace_buffer_start(p0,r0); 100 trace_buffer_init(p0,r0);
101 P0 = R1; 101 P0 = R1;
102 R0 = R1; 102 R0 = R1;
103 103
104#if CONFIG_DEBUG_KERNEL_START
105
106/*
107 * Set up a temporary Event Vector Table, so if something bad happens before
108 * the kernel is fully started, it doesn't vector off into the bootloaders
109 * table
110 */
111 P0.l = lo(EVT2);
112 P0.h = hi(EVT2);
113 P1.l = lo(EVT15);
114 P1.h = hi(EVT15);
115 P2.l = debug_kernel_start_trap;
116 P2.h = debug_kernel_start_trap;
117
118 RTS = P2;
119 RTI = P2;
120 RTX = P2;
121 RTN = P2;
122 RTE = P2;
123
124.Lfill_temp_vector_table:
125 [P0++] = P2; /* Core Event Vector Table */
126 CC = P0 == P1;
127 if !CC JUMP .Lfill_temp_vector_table
128 P0 = r0;
129 P1 = r0;
130 P2 = r0;
131
132#endif
133
134 p0.h = hi(FIO_MASKA_C); 104 p0.h = hi(FIO_MASKA_C);
135 p0.l = lo(FIO_MASKA_C); 105 p0.l = lo(FIO_MASKA_C);
136 r0 = 0xFFFF(Z); 106 r0 = 0xFFFF(Z);
@@ -144,38 +114,38 @@ ENTRY(__start)
144 ssync; 114 ssync;
145 115
146 /* Turn off the icache */ 116 /* Turn off the icache */
147 p0.l = (IMEM_CONTROL & 0xFFFF); 117 p0.l = LO(IMEM_CONTROL);
148 p0.h = (IMEM_CONTROL >> 16); 118 p0.h = HI(IMEM_CONTROL);
149 R1 = [p0]; 119 R1 = [p0];
150 R0 = ~ENICPLB; 120 R0 = ~ENICPLB;
151 R0 = R0 & R1; 121 R0 = R0 & R1;
152 122
153 /* Anomaly 05000125 */ 123 /* Anomaly 05000125 */
154#ifdef ANOMALY_05000125 124#if ANOMALY_05000125
155 CLI R2; 125 CLI R2;
156 SSYNC; 126 SSYNC;
157#endif 127#endif
158 [p0] = R0; 128 [p0] = R0;
159 SSYNC; 129 SSYNC;
160#ifdef ANOMALY_05000125 130#if ANOMALY_05000125
161 STI R2; 131 STI R2;
162#endif 132#endif
163 133
164 /* Turn off the dcache */ 134 /* Turn off the dcache */
165 p0.l = (DMEM_CONTROL & 0xFFFF); 135 p0.l = LO(DMEM_CONTROL);
166 p0.h = (DMEM_CONTROL >> 16); 136 p0.h = HI(DMEM_CONTROL);
167 R1 = [p0]; 137 R1 = [p0];
168 R0 = ~ENDCPLB; 138 R0 = ~ENDCPLB;
169 R0 = R0 & R1; 139 R0 = R0 & R1;
170 140
171 /* Anomaly 05000125 */ 141 /* Anomaly 05000125 */
172#ifdef ANOMALY_05000125 142#if ANOMALY_05000125
173 CLI R2; 143 CLI R2;
174 SSYNC; 144 SSYNC;
175#endif 145#endif
176 [p0] = R0; 146 [p0] = R0;
177 SSYNC; 147 SSYNC;
178#ifdef ANOMALY_05000125 148#if ANOMALY_05000125
179 STI R2; 149 STI R2;
180#endif 150#endif
181 151
@@ -211,6 +181,12 @@ ENTRY(__start)
211 fp = sp; 181 fp = sp;
212 usp = sp; 182 usp = sp;
213 183
184#ifdef CONFIG_EARLY_PRINTK
185 SP += -12;
186 call _init_early_exception_vectors;
187 SP += 12;
188#endif
189
214 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ 190 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
215 call _bf53x_relocate_l1_mem; 191 call _bf53x_relocate_l1_mem;
216#if CONFIG_BFIN_KERNEL_CLOCK 192#if CONFIG_BFIN_KERNEL_CLOCK
@@ -264,7 +240,7 @@ ENTRY(__start)
264 p0.l = .LWAIT_HERE; 240 p0.l = .LWAIT_HERE;
265 p0.h = .LWAIT_HERE; 241 p0.h = .LWAIT_HERE;
266 reti = p0; 242 reti = p0;
267#if defined(ANOMALY_05000281) 243#if ANOMALY_05000281
268 nop; nop; nop; 244 nop; nop; nop;
269#endif 245#endif
270 rti; 246 rti;
@@ -417,8 +393,8 @@ ENTRY(_start_dma_code)
417 w[p0] = r0.l; 393 w[p0] = r0.l;
418 ssync; 394 ssync;
419 395
420 p0.l = (EBIU_SDBCTL & 0xFFFF); 396 p0.l = LO(EBIU_SDBCTL);
421 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ 397 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
422 r0 = mem_SDBCTL; 398 r0 = mem_SDBCTL;
423 w[p0] = r0.l; 399 w[p0] = r0.l;
424 ssync; 400 ssync;
@@ -456,276 +432,6 @@ ENTRY(_start_dma_code)
456ENDPROC(_start_dma_code) 432ENDPROC(_start_dma_code)
457#endif /* CONFIG_BFIN_KERNEL_CLOCK */ 433#endif /* CONFIG_BFIN_KERNEL_CLOCK */
458 434
459ENTRY(_bfin_reset)
460 /* No more interrupts to be handled*/
461 CLI R6;
462 SSYNC;
463
464#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
465 p0.h = hi(FIO_INEN);
466 p0.l = lo(FIO_INEN);
467 r0.l = ~(1 << CONFIG_ENET_FLASH_PIN);
468 w[p0] = r0.l;
469
470 p0.h = hi(FIO_DIR);
471 p0.l = lo(FIO_DIR);
472 r0.l = (1 << CONFIG_ENET_FLASH_PIN);
473 w[p0] = r0.l;
474
475 p0.h = hi(FIO_FLAG_C);
476 p0.l = lo(FIO_FLAG_C);
477 r0.l = (1 << CONFIG_ENET_FLASH_PIN);
478 w[p0] = r0.l;
479#endif
480
481 /* Clear the IMASK register */
482 p0.h = hi(IMASK);
483 p0.l = lo(IMASK);
484 r0 = 0x0;
485 [p0] = r0;
486
487 /* Clear the ILAT register */
488 p0.h = hi(ILAT);
489 p0.l = lo(ILAT);
490 r0 = [p0];
491 [p0] = r0;
492 SSYNC;
493
494 /* make sure SYSCR is set to use BMODE */
495 P0.h = hi(SYSCR);
496 P0.l = lo(SYSCR);
497 R0.l = 0x0;
498 W[P0] = R0.l;
499 SSYNC;
500
501 /* issue a system soft reset */
502 P1.h = hi(SWRST);
503 P1.l = lo(SWRST);
504 R1.l = 0x0007;
505 W[P1] = R1;
506 SSYNC;
507
508 /* clear system soft reset */
509 R0.l = 0x0000;
510 W[P0] = R0;
511 SSYNC;
512
513 /* issue core reset */
514 raise 1;
515
516 RTS;
517ENDPROC(_bfin_reset)
518
519#if CONFIG_DEBUG_KERNEL_START
520debug_kernel_start_trap:
521 /* Set up a temp stack in L1 - SDRAM might not be working */
522 P0.L = lo(L1_DATA_A_START + 0x100);
523 P0.H = hi(L1_DATA_A_START + 0x100);
524 SP = P0;
525
526 /* Make sure the Clocks are the way I think they should be */
527 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
528 r0 = r0 << 9; /* Shift it over, */
529 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
530 r0 = r1 | r0;
531 r1 = PLL_BYPASS; /* Bypass the PLL? */
532 r1 = r1 << 8; /* Shift it over */
533 r0 = r1 | r0; /* add them all together */
534
535 p0.h = hi(PLL_CTL);
536 p0.l = lo(PLL_CTL); /* Load the address */
537 cli r2; /* Disable interrupts */
538 ssync;
539 w[p0] = r0.l; /* Set the value */
540 idle; /* Wait for the PLL to stablize */
541 sti r2; /* Enable interrupts */
542
543.Lcheck_again1:
544 p0.h = hi(PLL_STAT);
545 p0.l = lo(PLL_STAT);
546 R0 = W[P0](Z);
547 CC = BITTST(R0,5);
548 if ! CC jump .Lcheck_again1;
549
550 /* Configure SCLK & CCLK Dividers */
551 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
552 p0.h = hi(PLL_DIV);
553 p0.l = lo(PLL_DIV);
554 w[p0] = r0.l;
555 ssync;
556
557 /* Make sure UART is enabled - you can never be sure */
558
559/*
560 * Setup for console. Argument comes from the menuconfig
561 */
562
563#ifdef CONFIG_BAUD_9600
564#define CONSOLE_BAUD_RATE 9600
565#elif CONFIG_BAUD_19200
566#define CONSOLE_BAUD_RATE 19200
567#elif CONFIG_BAUD_38400
568#define CONSOLE_BAUD_RATE 38400
569#elif CONFIG_BAUD_57600
570#define CONSOLE_BAUD_RATE 57600
571#elif CONFIG_BAUD_115200
572#define CONSOLE_BAUD_RATE 115200
573#endif
574
575 p0.h = hi(UART_GCTL);
576 p0.l = lo(UART_GCTL);
577 r0 = 0x00(Z);
578 w[p0] = r0.L; /* To Turn off UART clocks */
579 ssync;
580
581 p0.h = hi(UART_LCR);
582 p0.l = lo(UART_LCR);
583 r0 = 0x83(Z);
584 w[p0] = r0.L; /* To enable DLL writes */
585 ssync;
586
587 R1 = (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_SCLK_DIV) / (CONSOLE_BAUD_RATE * 16));
588
589 p0.h = hi(UART_DLL);
590 p0.l = lo(UART_DLL);
591 r0 = 0xFF(Z);
592 r0 = R1 & R0;
593 w[p0] = r0.L;
594 ssync;
595
596 p0.h = hi(UART_DLH);
597 p0.l = lo(UART_DLH);
598 r1 >>= 8 ;
599 w[p0] = r1.L;
600 ssync;
601
602 p0.h = hi(UART_GCTL);
603 p0.l = lo(UART_GCTL);
604 r0 = 0x0(Z);
605 w[p0] = r0.L; /* To enable UART clock */
606 ssync;
607
608 p0.h = hi(UART_LCR);
609 p0.l = lo(UART_LCR);
610 r0 = 0x03(Z);
611 w[p0] = r0.L; /* To Turn on UART */
612 ssync;
613
614 p0.h = hi(UART_GCTL);
615 p0.l = lo(UART_GCTL);
616 r0 = 0x01(Z);
617 w[p0] = r0.L; /* To Turn on UART Clocks */
618 ssync;
619
620 P0.h = hi(UART_THR);
621 P0.l = lo(UART_THR);
622 P1.h = hi(UART_LSR);
623 P1.l = lo(UART_LSR);
624
625 R0.L = 'K';
626 call .Lwait_char;
627 R0.L='e';
628 call .Lwait_char;
629 R0.L='r';
630 call .Lwait_char;
631 R0.L='n'
632 call .Lwait_char;
633 R0.L='e'
634 call .Lwait_char;
635 R0.L='l';
636 call .Lwait_char;
637 R0.L=' ';
638 call .Lwait_char;
639 R0.L='c';
640 call .Lwait_char;
641 R0.L='r';
642 call .Lwait_char;
643 R0.L='a';
644 call .Lwait_char;
645 R0.L='s';
646 call .Lwait_char;
647 R0.L='h';
648 call .Lwait_char;
649 R0.L='\r';
650 call .Lwait_char;
651 R0.L='\n';
652 call .Lwait_char;
653
654 R0.L='S';
655 call .Lwait_char;
656 R0.L='E';
657 call .Lwait_char;
658 R0.L='Q'
659 call .Lwait_char;
660 R0.L='S'
661 call .Lwait_char;
662 R0.L='T';
663 call .Lwait_char;
664 R0.L='A';
665 call .Lwait_char;
666 R0.L='T';
667 call .Lwait_char;
668 R0.L='=';
669 call .Lwait_char;
670 R2 = SEQSTAT;
671 call .Ldump_reg;
672
673 R0.L=' ';
674 call .Lwait_char;
675 R0.L='R';
676 call .Lwait_char;
677 R0.L='E'
678 call .Lwait_char;
679 R0.L='T'
680 call .Lwait_char;
681 R0.L='X';
682 call .Lwait_char;
683 R0.L='=';
684 call .Lwait_char;
685 R2 = RETX;
686 call .Ldump_reg;
687
688 R0.L='\r';
689 call .Lwait_char;
690 R0.L='\n';
691 call .Lwait_char;
692
693.Ldebug_kernel_start_trap_done:
694 JUMP .Ldebug_kernel_start_trap_done;
695.Ldump_reg:
696 R3 = 32;
697 R4 = 0x0F;
698 R5 = ':'; /* one past 9 */
699
700.Ldump_reg2:
701 R0 = R2;
702 R3 += -4;
703 R0 >>>= R3;
704 R0 = R0 & R4;
705 R0 += 0x30;
706 CC = R0 <= R5;
707 if CC JUMP .Ldump_reg1;
708 R0 += 7;
709
710.Ldump_reg1:
711 R1.l = W[P1];
712 CC = BITTST(R1, 5);
713 if !CC JUMP .Ldump_reg1;
714 W[P0] = r0;
715
716 CC = R3 == 0;
717 if !CC JUMP .Ldump_reg2
718 RTS;
719
720.Lwait_char:
721 R1.l = W[P1];
722 CC = BITTST(R1, 5);
723 if !CC JUMP .Lwait_char;
724 W[P0] = r0;
725 RTS;
726
727#endif /* CONFIG_DEBUG_KERNEL_START */
728
729.data 435.data
730 436
731/* 437/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 10:46:59 -0500