diff options
Diffstat (limited to 'arch/blackfin/mach-bf533')
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/defBF532.h | 66 |
1 files changed, 0 insertions, 66 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index 02b328eb0e07..7e61fe762df2 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h | |||
| @@ -370,72 +370,6 @@ | |||
| 370 | /* System MMR Register Bits */ | 370 | /* System MMR Register Bits */ |
| 371 | /******************************************************************************* */ | 371 | /******************************************************************************* */ |
| 372 | 372 | ||
| 373 | /* ********************* PLL AND RESET MASKS ************************ */ | ||
| 374 | |||
| 375 | /* PLL_CTL Masks */ | ||
| 376 | #define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */ | ||
| 377 | #define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */ | ||
| 378 | #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ | ||
| 379 | #define PLL_OFF 0x0002 /* Shut off PLL clocks */ | ||
| 380 | #define STOPCK_OFF 0x0008 /* Core clock off */ | ||
| 381 | #define STOPCK 0x0008 /* Core Clock Off */ | ||
| 382 | #define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */ | ||
| 383 | #if !defined(__ADSPBF538__) | ||
| 384 | /* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */ | ||
| 385 | # define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ | ||
| 386 | # define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ | ||
| 387 | #endif | ||
| 388 | #define BYPASS 0x0100 /* Bypass the PLL */ | ||
| 389 | /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ | ||
| 390 | #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ | ||
| 391 | |||
| 392 | /* PLL_DIV Masks */ | ||
| 393 | #define SSEL 0x000F /* System Select */ | ||
| 394 | #define CSEL 0x0030 /* Core Select */ | ||
| 395 | |||
| 396 | #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ | ||
| 397 | |||
| 398 | #define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ | ||
| 399 | #define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ | ||
| 400 | #define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ | ||
| 401 | #define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ | ||
| 402 | /* PLL_DIV Macros */ | ||
| 403 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | ||
| 404 | |||
| 405 | /* PLL_STAT Masks */ | ||
| 406 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | ||
| 407 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | ||
| 408 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | ||
| 409 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | ||
| 410 | |||
| 411 | /* VR_CTL Masks */ | ||
| 412 | #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ | ||
| 413 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | ||
| 414 | #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ | ||
| 415 | #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ | ||
| 416 | #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ | ||
| 417 | |||
| 418 | #define GAIN 0x000C /* Voltage Level Gain */ | ||
| 419 | #define GAIN_5 0x0000 /* GAIN = 5 */ | ||
| 420 | #define GAIN_10 0x0004 /* GAIN = 10 */ | ||
| 421 | #define GAIN_20 0x0008 /* GAIN = 20 */ | ||
| 422 | #define GAIN_50 0x000C /* GAIN = 50 */ | ||
| 423 | |||
| 424 | #define VLEV 0x00F0 /* Internal Voltage Level */ | ||
| 425 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | ||
| 426 | #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ | ||
| 427 | #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ | ||
| 428 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ | ||
| 429 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ | ||
| 430 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ | ||
| 431 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ | ||
| 432 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ | ||
| 433 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ | ||
| 434 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | ||
| 435 | |||
| 436 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | ||
| 437 | #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ | ||
| 438 | |||
| 439 | /* CHIPID Masks */ | 373 | /* CHIPID Masks */ |
| 440 | #define CHIPID_VERSION 0xF0000000 | 374 | #define CHIPID_VERSION 0xF0000000 |
| 441 | #define CHIPID_FAMILY 0x0FFFF000 | 375 | #define CHIPID_FAMILY 0x0FFFF000 |