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-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h1
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h2
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 70a0ad69c610..cd83db2fb1a1 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -335,6 +335,7 @@
335#define ANOMALY_05000323 (0) 335#define ANOMALY_05000323 (0)
336#define ANOMALY_05000353 (1) 336#define ANOMALY_05000353 (1)
337#define ANOMALY_05000362 (1) 337#define ANOMALY_05000362 (1)
338#define ANOMALY_05000364 (0)
338#define ANOMALY_05000380 (0) 339#define ANOMALY_05000380 (0)
339#define ANOMALY_05000386 (1) 340#define ANOMALY_05000386 (1)
340#define ANOMALY_05000389 (0) 341#define ANOMALY_05000389 (0)
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index a3789d7ccf8c..4062e24e759b 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -53,7 +53,7 @@
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) 53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) 54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55 55
56#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) 56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) 57#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) 58#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)