diff options
Diffstat (limited to 'arch/blackfin/mach-bf533/include/mach/defBF532.h')
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/defBF532.h | 92 |
1 files changed, 0 insertions, 92 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index e9ff491c0953..04acf1ed10f9 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h | |||
| @@ -509,98 +509,6 @@ | |||
| 509 | #define IREN_P 0x01 | 509 | #define IREN_P 0x01 |
| 510 | #define UCEN_P 0x00 | 510 | #define UCEN_P 0x00 |
| 511 | 511 | ||
| 512 | /* ********** SERIAL PORT MASKS ********************** */ | ||
| 513 | |||
| 514 | /* SPORTx_TCR1 Masks */ | ||
| 515 | #define TSPEN 0x0001 /* TX enable */ | ||
| 516 | #define ITCLK 0x0002 /* Internal TX Clock Select */ | ||
| 517 | #define TDTYPE 0x000C /* TX Data Formatting Select */ | ||
| 518 | #define DTYPE_NORM 0x0000 /* Data Format Normal */ | ||
| 519 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 520 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 521 | #define TLSBIT 0x0010 /* TX Bit Order */ | ||
| 522 | #define ITFS 0x0200 /* Internal TX Frame Sync Select */ | ||
| 523 | #define TFSR 0x0400 /* TX Frame Sync Required Select */ | ||
| 524 | #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ | ||
| 525 | #define LTFS 0x1000 /* Low TX Frame Sync Select */ | ||
| 526 | #define LATFS 0x2000 /* Late TX Frame Sync Select */ | ||
| 527 | #define TCKFE 0x4000 /* TX Clock Falling Edge Select */ | ||
| 528 | |||
| 529 | /* SPORTx_TCR2 Masks */ | ||
| 530 | #if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \ | ||
| 531 | defined(__ADSPBF533__) | ||
| 532 | # define SLEN 0x001F /*TX Word Length */ | ||
| 533 | #else | ||
| 534 | # define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ | ||
| 535 | #endif | ||
| 536 | #define TXSE 0x0100 /*TX Secondary Enable */ | ||
| 537 | #define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ | ||
| 538 | #define TRFST 0x0400 /*TX Right-First Data Order */ | ||
| 539 | |||
| 540 | /* SPORTx_RCR1 Masks */ | ||
| 541 | #define RSPEN 0x0001 /* RX enable */ | ||
| 542 | #define IRCLK 0x0002 /* Internal RX Clock Select */ | ||
| 543 | #define RDTYPE 0x000C /* RX Data Formatting Select */ | ||
| 544 | #define DTYPE_NORM 0x0000 /* no companding */ | ||
| 545 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 546 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 547 | #define RLSBIT 0x0010 /* RX Bit Order */ | ||
| 548 | #define IRFS 0x0200 /* Internal RX Frame Sync Select */ | ||
| 549 | #define RFSR 0x0400 /* RX Frame Sync Required Select */ | ||
| 550 | #define LRFS 0x1000 /* Low RX Frame Sync Select */ | ||
| 551 | #define LARFS 0x2000 /* Late RX Frame Sync Select */ | ||
| 552 | #define RCKFE 0x4000 /* RX Clock Falling Edge Select */ | ||
| 553 | |||
| 554 | /* SPORTx_RCR2 Masks */ | ||
| 555 | /* SLEN defined above */ | ||
| 556 | #define RXSE 0x0100 /*RX Secondary Enable */ | ||
| 557 | #define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ | ||
| 558 | #define RRFST 0x0400 /*Right-First Data Order */ | ||
| 559 | |||
| 560 | /*SPORTx_STAT Masks */ | ||
| 561 | #define RXNE 0x0001 /*RX FIFO Not Empty Status */ | ||
| 562 | #define RUVF 0x0002 /*RX Underflow Status */ | ||
| 563 | #define ROVF 0x0004 /*RX Overflow Status */ | ||
| 564 | #define TXF 0x0008 /*TX FIFO Full Status */ | ||
| 565 | #define TUVF 0x0010 /*TX Underflow Status */ | ||
| 566 | #define TOVF 0x0020 /*TX Overflow Status */ | ||
| 567 | #define TXHRE 0x0040 /*TX Hold Register Empty */ | ||
| 568 | |||
| 569 | /*SPORTx_MCMC1 Masks */ | ||
| 570 | #define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ | ||
| 571 | #define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ | ||
| 572 | /* SPORTx_MCMC1 Macros */ | ||
| 573 | #define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ | ||
| 574 | /* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */ | ||
| 575 | #define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ | ||
| 576 | |||
| 577 | /*SPORTx_MCMC2 Masks */ | ||
| 578 | #define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ | ||
| 579 | #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ | ||
| 580 | #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ | ||
| 581 | #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ | ||
| 582 | #define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ | ||
| 583 | #define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ | ||
| 584 | #define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ | ||
| 585 | #define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ | ||
| 586 | #define MFD 0x0000F000 /*Multichannel Frame Delay */ | ||
| 587 | #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ | ||
| 588 | #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ | ||
| 589 | #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ | ||
| 590 | #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ | ||
| 591 | #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ | ||
| 592 | #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ | ||
| 593 | #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ | ||
| 594 | #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ | ||
| 595 | #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ | ||
| 596 | #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ | ||
| 597 | #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ | ||
| 598 | #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ | ||
| 599 | #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ | ||
| 600 | #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ | ||
| 601 | #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ | ||
| 602 | #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ | ||
| 603 | |||
| 604 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ | 512 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ |
| 605 | 513 | ||
| 606 | /* PPI_CONTROL Masks */ | 514 | /* PPI_CONTROL Masks */ |