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Diffstat (limited to 'arch/blackfin/mach-bf533/include/mach/cdefBF532.h')
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index d7b08f638ea4..bbc3c8386d48 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -684,10 +684,10 @@
684static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ 684static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
685{ \ 685{ \
686 unsigned long flags; \ 686 unsigned long flags; \
687 local_irq_save(flags); \ 687 local_irq_save_hw(flags); \
688 bfin_write16(FIO_FLAG_##name, val); \ 688 bfin_write16(FIO_FLAG_##name, val); \
689 bfin_read_CHIPID(); \ 689 bfin_read_CHIPID(); \
690 local_irq_restore(flags); \ 690 local_irq_restore_hw(flags); \
691} 691}
692BFIN_WRITE_FIO_FLAG(D) 692BFIN_WRITE_FIO_FLAG(D)
693BFIN_WRITE_FIO_FLAG(C) 693BFIN_WRITE_FIO_FLAG(C)
@@ -699,10 +699,10 @@ static inline u16 bfin_read_FIO_FLAG_##name(void) \
699{ \ 699{ \
700 unsigned long flags; \ 700 unsigned long flags; \
701 u16 ret; \ 701 u16 ret; \
702 local_irq_save(flags); \ 702 local_irq_save_hw(flags); \
703 ret = bfin_read16(FIO_FLAG_##name); \ 703 ret = bfin_read16(FIO_FLAG_##name); \
704 bfin_read_CHIPID(); \ 704 bfin_read_CHIPID(); \
705 local_irq_restore(flags); \ 705 local_irq_restore_hw(flags); \
706 return ret; \ 706 return ret; \
707} 707}
708BFIN_READ_FIO_FLAG(D) 708BFIN_READ_FIO_FLAG(D)
@@ -729,7 +729,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
729 if (val == bfin_read_PLL_CTL()) 729 if (val == bfin_read_PLL_CTL())
730 return; 730 return;
731 731
732 local_irq_save(flags); 732 local_irq_save_hw(flags);
733 /* Enable the PLL Wakeup bit in SIC IWR */ 733 /* Enable the PLL Wakeup bit in SIC IWR */
734 iwr = bfin_read32(SIC_IWR); 734 iwr = bfin_read32(SIC_IWR);
735 /* Only allow PPL Wakeup) */ 735 /* Only allow PPL Wakeup) */
@@ -740,7 +740,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
740 asm("IDLE;"); 740 asm("IDLE;");
741 741
742 bfin_write32(SIC_IWR, iwr); 742 bfin_write32(SIC_IWR, iwr);
743 local_irq_restore(flags); 743 local_irq_restore_hw(flags);
744} 744}
745 745
746/* Writing to VR_CTL initiates a PLL relock sequence. */ 746/* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -751,7 +751,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
751 if (val == bfin_read_VR_CTL()) 751 if (val == bfin_read_VR_CTL())
752 return; 752 return;
753 753
754 local_irq_save(flags); 754 local_irq_save_hw(flags);
755 /* Enable the PLL Wakeup bit in SIC IWR */ 755 /* Enable the PLL Wakeup bit in SIC IWR */
756 iwr = bfin_read32(SIC_IWR); 756 iwr = bfin_read32(SIC_IWR);
757 /* Only allow PPL Wakeup) */ 757 /* Only allow PPL Wakeup) */
@@ -762,7 +762,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
762 asm("IDLE;"); 762 asm("IDLE;");
763 763
764 bfin_write32(SIC_IWR, iwr); 764 bfin_write32(SIC_IWR, iwr);
765 local_irq_restore(flags); 765 local_irq_restore_hw(flags);
766} 766}
767 767
768#endif /* _CDEF_BF532_H */ 768#endif /* _CDEF_BF532_H */