diff options
Diffstat (limited to 'arch/blackfin/mach-bf533/include/mach/anomaly.h')
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/anomaly.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 78f872187918..72aa59440f82 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h | |||
@@ -5,13 +5,13 @@ | |||
5 | * and can be replaced with that version at any time | 5 | * and can be replaced with that version at any time |
6 | * DO NOT EDIT THIS FILE | 6 | * DO NOT EDIT THIS FILE |
7 | * | 7 | * |
8 | * Copyright 2004-2010 Analog Devices Inc. | 8 | * Copyright 2004-2011 Analog Devices Inc. |
9 | * Licensed under the ADI BSD license. | 9 | * Licensed under the ADI BSD license. |
10 | * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd | 10 | * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd |
11 | */ | 11 | */ |
12 | 12 | ||
13 | /* This file should be up to date with: | 13 | /* This file should be up to date with: |
14 | * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List | 14 | * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #ifndef _MACH_ANOMALY_H_ | 17 | #ifndef _MACH_ANOMALY_H_ |
@@ -206,6 +206,10 @@ | |||
206 | #define ANOMALY_05000443 (1) | 206 | #define ANOMALY_05000443 (1) |
207 | /* False Hardware Error when RETI Points to Invalid Memory */ | 207 | /* False Hardware Error when RETI Points to Invalid Memory */ |
208 | #define ANOMALY_05000461 (1) | 208 | #define ANOMALY_05000461 (1) |
209 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ | ||
210 | #define ANOMALY_05000462 (1) | ||
211 | /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ | ||
212 | #define ANOMALY_05000471 (1) | ||
209 | /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ | 213 | /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ |
210 | #define ANOMALY_05000473 (1) | 214 | #define ANOMALY_05000473 (1) |
211 | /* Possible Lockup Condition whem Modifying PLL from External Memory */ | 215 | /* Possible Lockup Condition whem Modifying PLL from External Memory */ |
@@ -351,12 +355,14 @@ | |||
351 | #define ANOMALY_05000362 (1) | 355 | #define ANOMALY_05000362 (1) |
352 | #define ANOMALY_05000364 (0) | 356 | #define ANOMALY_05000364 (0) |
353 | #define ANOMALY_05000380 (0) | 357 | #define ANOMALY_05000380 (0) |
358 | #define ANOMALY_05000383 (0) | ||
354 | #define ANOMALY_05000386 (1) | 359 | #define ANOMALY_05000386 (1) |
355 | #define ANOMALY_05000389 (0) | 360 | #define ANOMALY_05000389 (0) |
356 | #define ANOMALY_05000412 (0) | 361 | #define ANOMALY_05000412 (0) |
357 | #define ANOMALY_05000430 (0) | 362 | #define ANOMALY_05000430 (0) |
358 | #define ANOMALY_05000432 (0) | 363 | #define ANOMALY_05000432 (0) |
359 | #define ANOMALY_05000435 (0) | 364 | #define ANOMALY_05000435 (0) |
365 | #define ANOMALY_05000440 (0) | ||
360 | #define ANOMALY_05000447 (0) | 366 | #define ANOMALY_05000447 (0) |
361 | #define ANOMALY_05000448 (0) | 367 | #define ANOMALY_05000448 (0) |
362 | #define ANOMALY_05000456 (0) | 368 | #define ANOMALY_05000456 (0) |
@@ -364,6 +370,7 @@ | |||
364 | #define ANOMALY_05000465 (0) | 370 | #define ANOMALY_05000465 (0) |
365 | #define ANOMALY_05000467 (0) | 371 | #define ANOMALY_05000467 (0) |
366 | #define ANOMALY_05000474 (0) | 372 | #define ANOMALY_05000474 (0) |
373 | #define ANOMALY_05000480 (0) | ||
367 | #define ANOMALY_05000485 (0) | 374 | #define ANOMALY_05000485 (0) |
368 | 375 | ||
369 | #endif | 376 | #endif |