diff options
Diffstat (limited to 'arch/blackfin/mach-bf533/include/mach/anomaly.h')
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/anomaly.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 0d3a03429fb9..1cf893e2e55b 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * File: include/asm-blackfin/mach-bf533/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf533/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
4 | * | 4 | * |
5 | * Copyright (C) 2004-2008 Analog Devices Inc. | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
7 | */ | 7 | */ |
8 | 8 | ||
@@ -160,7 +160,7 @@ | |||
160 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) | 160 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) |
161 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ | 161 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ |
162 | #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) | 162 | #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) |
163 | /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ | 163 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ |
164 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) | 164 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) |
165 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ | 165 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ |
166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) | 166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) |
@@ -278,9 +278,12 @@ | |||
278 | #define ANOMALY_05000266 (0) | 278 | #define ANOMALY_05000266 (0) |
279 | #define ANOMALY_05000323 (0) | 279 | #define ANOMALY_05000323 (0) |
280 | #define ANOMALY_05000353 (1) | 280 | #define ANOMALY_05000353 (1) |
281 | #define ANOMALY_05000380 (0) | ||
281 | #define ANOMALY_05000386 (1) | 282 | #define ANOMALY_05000386 (1) |
282 | #define ANOMALY_05000412 (0) | 283 | #define ANOMALY_05000412 (0) |
283 | #define ANOMALY_05000432 (0) | 284 | #define ANOMALY_05000432 (0) |
284 | #define ANOMALY_05000435 (0) | 285 | #define ANOMALY_05000435 (0) |
286 | #define ANOMALY_05000447 (0) | ||
287 | #define ANOMALY_05000448 (0) | ||
285 | 288 | ||
286 | #endif | 289 | #endif |