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-rw-r--r--arch/blackfin/mach-bf533/head.S12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 5aeffd06fe71..69da0e8b7732 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -144,8 +144,8 @@ ENTRY(__start)
144 ssync; 144 ssync;
145 145
146 /* Turn off the icache */ 146 /* Turn off the icache */
147 p0.l = (IMEM_CONTROL & 0xFFFF); 147 p0.l = LO(IMEM_CONTROL);
148 p0.h = (IMEM_CONTROL >> 16); 148 p0.h = HI(IMEM_CONTROL);
149 R1 = [p0]; 149 R1 = [p0];
150 R0 = ~ENICPLB; 150 R0 = ~ENICPLB;
151 R0 = R0 & R1; 151 R0 = R0 & R1;
@@ -162,8 +162,8 @@ ENTRY(__start)
162#endif 162#endif
163 163
164 /* Turn off the dcache */ 164 /* Turn off the dcache */
165 p0.l = (DMEM_CONTROL & 0xFFFF); 165 p0.l = LO(DMEM_CONTROL);
166 p0.h = (DMEM_CONTROL >> 16); 166 p0.h = HI(DMEM_CONTROL);
167 R1 = [p0]; 167 R1 = [p0];
168 R0 = ~ENDCPLB; 168 R0 = ~ENDCPLB;
169 R0 = R0 & R1; 169 R0 = R0 & R1;
@@ -417,8 +417,8 @@ ENTRY(_start_dma_code)
417 w[p0] = r0.l; 417 w[p0] = r0.l;
418 ssync; 418 ssync;
419 419
420 p0.l = (EBIU_SDBCTL & 0xFFFF); 420 p0.l = LO(EBIU_SDBCTL);
421 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ 421 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
422 r0 = mem_SDBCTL; 422 r0 = mem_SDBCTL;
423 w[p0] = r0.l; 423 w[p0] = r0.l;
424 ssync; 424 ssync;