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1/*
2 * File: arch/blackfin/mach-bf533/head.S
3 * Based on:
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: bf533 startup file
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <asm/blackfin.h>
32#if CONFIG_BFIN_KERNEL_CLOCK
33#include <asm/mach/mem_init.h>
34#endif
35#if CONFIG_DEBUG_KERNEL_START
36#include <asm/mach-common/def_LPBlackfin.h>
37#endif
38
39.global __rambase
40.global __ramstart
41.global __ramend
42.extern ___bss_stop
43.extern ___bss_start
44.extern _bf53x_relocate_l1_mem
45
46#define INITIAL_STACK 0xFFB01000
47
48.text
49
50ENTRY(__start)
51ENTRY(__stext)
52 /* R0: argument of command line string, passed from uboot, save it */
53 R7 = R0;
54 /* Set the SYSCFG register */
55 R0 = 0x36;
56 /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
57 SYSCFG = R0;
58 R0 = 0;
59
60 /*Clear Out All the data and pointer Registers*/
61 R1 = R0;
62 R2 = R0;
63 R3 = R0;
64 R4 = R0;
65 R5 = R0;
66 R6 = R0;
67
68 P0 = R0;
69 P1 = R0;
70 P2 = R0;
71 P3 = R0;
72 P4 = R0;
73 P5 = R0;
74
75 LC0 = r0;
76 LC1 = r0;
77 L0 = r0;
78 L1 = r0;
79 L2 = r0;
80 L3 = r0;
81
82 /* Clear Out All the DAG Registers*/
83 B0 = r0;
84 B1 = r0;
85 B2 = r0;
86 B3 = r0;
87
88 I0 = r0;
89 I1 = r0;
90 I2 = r0;
91 I3 = r0;
92
93 M0 = r0;
94 M1 = r0;
95 M2 = r0;
96 M3 = r0;
97
98#if CONFIG_DEBUG_KERNEL_START
99
100/*
101 * Set up a temporary Event Vector Table, so if something bad happens before
102 * the kernel is fully started, it doesn't vector off into the bootloaders
103 * table
104 */
105 P0.l = lo(EVT2);
106 P0.h = hi(EVT2);
107 P1.l = lo(EVT15);
108 P1.h = hi(EVT15);
109 P2.l = debug_kernel_start_trap;
110 P2.h = debug_kernel_start_trap;
111
112 RTS = P2;
113 RTI = P2;
114 RTX = P2;
115 RTN = P2;
116 RTE = P2;
117
118.Lfill_temp_vector_table:
119 [P0++] = P2; /* Core Event Vector Table */
120 CC = P0 == P1;
121 if !CC JUMP .Lfill_temp_vector_table
122 P0 = r0;
123 P1 = r0;
124 P2 = r0;
125
126#endif
127
128 p0.h = hi(FIO_MASKA_C);
129 p0.l = lo(FIO_MASKA_C);
130 r0 = 0xFFFF(Z);
131 w[p0] = r0.L; /* Disable all interrupts */
132 ssync;
133
134 p0.h = hi(FIO_MASKB_C);
135 p0.l = lo(FIO_MASKB_C);
136 r0 = 0xFFFF(Z);
137 w[p0] = r0.L; /* Disable all interrupts */
138 ssync;
139
140 /* Turn off the icache */
141 p0.l = (IMEM_CONTROL & 0xFFFF);
142 p0.h = (IMEM_CONTROL >> 16);
143 R1 = [p0];
144 R0 = ~ENICPLB;
145 R0 = R0 & R1;
146
147 /* Anomaly 05000125 */
148#ifdef ANOMALY_05000125
149 CLI R2;
150 SSYNC;
151#endif
152 [p0] = R0;
153 SSYNC;
154#ifdef ANOMALY_05000125
155 STI R2;
156#endif
157
158 /* Turn off the dcache */
159 p0.l = (DMEM_CONTROL & 0xFFFF);
160 p0.h = (DMEM_CONTROL >> 16);
161 R1 = [p0];
162 R0 = ~ENDCPLB;
163 R0 = R0 & R1;
164
165 /* Anomaly 05000125 */
166#ifdef ANOMALY_05000125
167 CLI R2;
168 SSYNC;
169#endif
170 [p0] = R0;
171 SSYNC;
172#ifdef ANOMALY_05000125
173 STI R2;
174#endif
175
176 /* Initialise UART */
177 p0.h = hi(UART_LCR);
178 p0.l = lo(UART_LCR);
179 r0 = 0x0(Z);
180 w[p0] = r0.L; /* To enable DLL writes */
181 ssync;
182
183 p0.h = hi(UART_DLL);
184 p0.l = lo(UART_DLL);
185 r0 = 0x0(Z);
186 w[p0] = r0.L;
187 ssync;
188
189 p0.h = hi(UART_DLH);
190 p0.l = lo(UART_DLH);
191 r0 = 0x00(Z);
192 w[p0] = r0.L;
193 ssync;
194
195 p0.h = hi(UART_GCTL);
196 p0.l = lo(UART_GCTL);
197 r0 = 0x0(Z);
198 w[p0] = r0.L; /* To enable UART clock */
199 ssync;
200
201 /* Initialize stack pointer */
202 sp.l = lo(INITIAL_STACK);
203 sp.h = hi(INITIAL_STACK);
204 fp = sp;
205 usp = sp;
206
207 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
208 call _bf53x_relocate_l1_mem;
209#if CONFIG_BFIN_KERNEL_CLOCK
210 call _start_dma_code;
211#endif
212
213 /* Code for initializing Async memory banks */
214
215 p2.h = hi(EBIU_AMBCTL1);
216 p2.l = lo(EBIU_AMBCTL1);
217 r0.h = hi(AMBCTL1VAL);
218 r0.l = lo(AMBCTL1VAL);
219 [p2] = r0;
220 ssync;
221
222 p2.h = hi(EBIU_AMBCTL0);
223 p2.l = lo(EBIU_AMBCTL0);
224 r0.h = hi(AMBCTL0VAL);
225 r0.l = lo(AMBCTL0VAL);
226 [p2] = r0;
227 ssync;
228
229 p2.h = hi(EBIU_AMGCTL);
230 p2.l = lo(EBIU_AMGCTL);
231 r0 = AMGCTLVAL;
232 w[p2] = r0;
233 ssync;
234
235 /* This section keeps the processor in supervisor mode
236 * during kernel boot. Switches to user mode at end of boot.
237 * See page 3-9 of Hardware Reference manual for documentation.
238 */
239
240 /* EVT15 = _real_start */
241
242 p0.l = lo(EVT15);
243 p0.h = hi(EVT15);
244 p1.l = _real_start;
245 p1.h = _real_start;
246 [p0] = p1;
247 csync;
248
249 p0.l = lo(IMASK);
250 p0.h = hi(IMASK);
251 p1.l = IMASK_IVG15;
252 p1.h = 0x0;
253 [p0] = p1;
254 csync;
255
256 raise 15;
257 p0.l = .LWAIT_HERE;
258 p0.h = .LWAIT_HERE;
259 reti = p0;
260#if defined(ANOMALY_05000281)
261 nop; nop; nop;
262#endif
263 rti;
264
265.LWAIT_HERE:
266 jump .LWAIT_HERE;
267
268ENTRY(_real_start)
269 [ -- sp ] = reti;
270 p0.l = lo(WDOG_CTL);
271 p0.h = hi(WDOG_CTL);
272 r0 = 0xAD6(z);
273 w[p0] = r0; /* watchdog off for now */
274 ssync;
275
276 /* Code update for BSS size == 0
277 * Zero out the bss region.
278 */
279
280 p1.l = ___bss_start;
281 p1.h = ___bss_start;
282 p2.l = ___bss_stop;
283 p2.h = ___bss_stop;
284 r0 = 0;
285 p2 -= p1;
286 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
287.L_clear_bss:
288 B[p1++] = r0;
289
290 /* In case there is a NULL pointer reference
291 * Zero out region before stext
292 */
293
294 p1.l = 0x0;
295 p1.h = 0x0;
296 r0.l = __stext;
297 r0.h = __stext;
298 r0 = r0 >> 1;
299 p2 = r0;
300 r0 = 0;
301 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
302.L_clear_zero:
303 W[p1++] = r0;
304
305/* pass the uboot arguments to the global value command line */
306 R0 = R7;
307 call _cmdline_init;
308
309 p1.l = __rambase;
310 p1.h = __rambase;
311 r0.l = __sdata;
312 r0.h = __sdata;
313 [p1] = r0;
314
315 p1.l = __ramstart;
316 p1.h = __ramstart;
317 p3.l = ___bss_stop;
318 p3.h = ___bss_stop;
319
320 r1 = p3;
321 [p1] = r1;
322
323 /*
324 * load the current thread pointer and stack
325 */
326 r1.l = _init_thread_union;
327 r1.h = _init_thread_union;
328
329 r2.l = 0x2000;
330 r2.h = 0x0000;
331 r1 = r1 + r2;
332 sp = r1;
333 usp = sp;
334 fp = sp;
335 call _start_kernel;
336.L_exit:
337 jump.s .L_exit;
338
339.section .l1.text
340#if CONFIG_BFIN_KERNEL_CLOCK
341ENTRY(_start_dma_code)
342 p0.h = hi(SIC_IWR);
343 p0.l = lo(SIC_IWR);
344 r0.l = 0x1;
345 r0.h = 0x0;
346 [p0] = r0;
347 SSYNC;
348
349 /*
350 * Set PLL_CTL
351 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
352 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
353 * - [7] = output delay (add 200ps of delay to mem signals)
354 * - [6] = input delay (add 200ps of input delay to mem signals)
355 * - [5] = PDWN : 1=All Clocks off
356 * - [3] = STOPCK : 1=Core Clock off
357 * - [1] = PLL_OFF : 1=Disable Power to PLL
358 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
359 * all other bits set to zero
360 */
361
362 p0.h = hi(PLL_LOCKCNT);
363 p0.l = lo(PLL_LOCKCNT);
364 r0 = 0x300(Z);
365 w[p0] = r0.l;
366 ssync;
367
368 P2.H = hi(EBIU_SDGCTL);
369 P2.L = lo(EBIU_SDGCTL);
370 R0 = [P2];
371 BITSET (R0, 24);
372 [P2] = R0;
373 SSYNC;
374
375 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
376 r0 = r0 << 9; /* Shift it over, */
377 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
378 r0 = r1 | r0;
379 r1 = PLL_BYPASS; /* Bypass the PLL? */
380 r1 = r1 << 8; /* Shift it over */
381 r0 = r1 | r0; /* add them all together */
382
383 p0.h = hi(PLL_CTL);
384 p0.l = lo(PLL_CTL); /* Load the address */
385 cli r2; /* Disable interrupts */
386 ssync;
387 w[p0] = r0.l; /* Set the value */
388 idle; /* Wait for the PLL to stablize */
389 sti r2; /* Enable interrupts */
390
391.Lcheck_again:
392 p0.h = hi(PLL_STAT);
393 p0.l = lo(PLL_STAT);
394 R0 = W[P0](Z);
395 CC = BITTST(R0,5);
396 if ! CC jump .Lcheck_again;
397
398 /* Configure SCLK & CCLK Dividers */
399 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
400 p0.h = hi(PLL_DIV);
401 p0.l = lo(PLL_DIV);
402 w[p0] = r0.l;
403 ssync;
404
405 p0.l = lo(EBIU_SDRRC);
406 p0.h = hi(EBIU_SDRRC);
407 r0 = mem_SDRRC;
408 w[p0] = r0.l;
409 ssync;
410
411 p0.l = (EBIU_SDBCTL & 0xFFFF);
412 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
413 r0 = mem_SDBCTL;
414 w[p0] = r0.l;
415 ssync;
416
417 P2.H = hi(EBIU_SDGCTL);
418 P2.L = lo(EBIU_SDGCTL);
419 R0 = [P2];
420 BITCLR (R0, 24);
421 p0.h = hi(EBIU_SDSTAT);
422 p0.l = lo(EBIU_SDSTAT);
423 r2.l = w[p0];
424 cc = bittst(r2,3);
425 if !cc jump .Lskip;
426 NOP;
427 BITSET (R0, 23);
428.Lskip:
429 [P2] = R0;
430 SSYNC;
431
432 R0.L = lo(mem_SDGCTL);
433 R0.H = hi(mem_SDGCTL);
434 R1 = [p2];
435 R1 = R1 | R0;
436 [P2] = R1;
437 SSYNC;
438
439 p0.h = hi(SIC_IWR);
440 p0.l = lo(SIC_IWR);
441 r0.l = lo(IWR_ENABLE_ALL)
442 r0.h = hi(IWR_ENABLE_ALL)
443 [p0] = r0;
444 SSYNC;
445
446 RTS;
447#endif /* CONFIG_BFIN_KERNEL_CLOCK */
448
449ENTRY(_bfin_reset)
450 /* No more interrupts to be handled*/
451 CLI R6;
452 SSYNC;
453
454#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
455 p0.h = hi(FIO_INEN);
456 p0.l = lo(FIO_INEN);
457 r0.l = ~(1 << CONFIG_ENET_FLASH_PIN);
458 w[p0] = r0.l;
459
460 p0.h = hi(FIO_DIR);
461 p0.l = lo(FIO_DIR);
462 r0.l = (1 << CONFIG_ENET_FLASH_PIN);
463 w[p0] = r0.l;
464
465 p0.h = hi(FIO_FLAG_C);
466 p0.l = lo(FIO_FLAG_C);
467 r0.l = (1 << CONFIG_ENET_FLASH_PIN);
468 w[p0] = r0.l;
469#endif
470
471 /* Clear the bits 13-15 in SWRST if they werent cleared */
472 p0.h = hi(SWRST);
473 p0.l = lo(SWRST);
474 csync;
475 r0.l = w[p0];
476
477 /* Clear the IMASK register */
478 p0.h = hi(IMASK);
479 p0.l = lo(IMASK);
480 r0 = 0x0;
481 [p0] = r0;
482
483 /* Clear the ILAT register */
484 p0.h = hi(ILAT);
485 p0.l = lo(ILAT);
486 r0 = [p0];
487 [p0] = r0;
488 SSYNC;
489
490 /* Disable the WDOG TIMER */
491 p0.h = hi(WDOG_CTL);
492 p0.l = lo(WDOG_CTL);
493 r0.l = 0xAD6;
494 w[p0] = r0.l;
495 SSYNC;
496
497 /* Clear the sticky bit incase it is already set */
498 p0.h = hi(WDOG_CTL);
499 p0.l = lo(WDOG_CTL);
500 r0.l = 0x8AD6;
501 w[p0] = r0.l;
502 SSYNC;
503
504 /* Program the count value */
505 R0.l = 0x100;
506 R0.h = 0x0;
507 P0.h = hi(WDOG_CNT);
508 P0.l = lo(WDOG_CNT);
509 [P0] = R0;
510 SSYNC;
511
512 /* Program WDOG_STAT if necessary */
513 P0.h = hi(WDOG_CTL);
514 P0.l = lo(WDOG_CTL);
515 R0 = W[P0](Z);
516 CC = BITTST(R0,1);
517 if !CC JUMP .LWRITESTAT;
518 CC = BITTST(R0,2);
519 if !CC JUMP .LWRITESTAT;
520 JUMP .LSKIP_WRITE;
521
522.LWRITESTAT:
523 /* When watch dog timer is enabled, a write to STAT will load the contents of CNT to STAT */
524 R0 = 0x0000(z);
525 P0.h = hi(WDOG_STAT);
526 P0.l = lo(WDOG_STAT)
527 [P0] = R0;
528 SSYNC;
529
530.LSKIP_WRITE:
531 /* Enable the reset event */
532 P0.h = hi(WDOG_CTL);
533 P0.l = lo(WDOG_CTL);
534 R0 = W[P0](Z);
535 BITCLR(R0,1);
536 BITCLR(R0,2);
537 W[P0] = R0.L;
538 SSYNC;
539 NOP;
540
541 /* Enable the wdog counter */
542 R0 = W[P0](Z);
543 BITCLR(R0,4);
544 W[P0] = R0.L;
545 SSYNC;
546
547 IDLE;
548
549 RTS;
550
551#if CONFIG_DEBUG_KERNEL_START
552debug_kernel_start_trap:
553 /* Set up a temp stack in L1 - SDRAM might not be working */
554 P0.L = lo(L1_DATA_A_START + 0x100);
555 P0.H = hi(L1_DATA_A_START + 0x100);
556 SP = P0;
557
558 /* Make sure the Clocks are the way I think they should be */
559 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
560 r0 = r0 << 9; /* Shift it over, */
561 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
562 r0 = r1 | r0;
563 r1 = PLL_BYPASS; /* Bypass the PLL? */
564 r1 = r1 << 8; /* Shift it over */
565 r0 = r1 | r0; /* add them all together */
566
567 p0.h = hi(PLL_CTL);
568 p0.l = lo(PLL_CTL); /* Load the address */
569 cli r2; /* Disable interrupts */
570 ssync;
571 w[p0] = r0.l; /* Set the value */
572 idle; /* Wait for the PLL to stablize */
573 sti r2; /* Enable interrupts */
574
575.Lcheck_again1:
576 p0.h = hi(PLL_STAT);
577 p0.l = lo(PLL_STAT);
578 R0 = W[P0](Z);
579 CC = BITTST(R0,5);
580 if ! CC jump .Lcheck_again1;
581
582 /* Configure SCLK & CCLK Dividers */
583 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
584 p0.h = hi(PLL_DIV);
585 p0.l = lo(PLL_DIV);
586 w[p0] = r0.l;
587 ssync;
588
589 /* Make sure UART is enabled - you can never be sure */
590
591/*
592 * Setup for console. Argument comes from the menuconfig
593 */
594
595#ifdef CONFIG_BAUD_9600
596#define CONSOLE_BAUD_RATE 9600
597#elif CONFIG_BAUD_19200
598#define CONSOLE_BAUD_RATE 19200
599#elif CONFIG_BAUD_38400
600#define CONSOLE_BAUD_RATE 38400
601#elif CONFIG_BAUD_57600
602#define CONSOLE_BAUD_RATE 57600
603#elif CONFIG_BAUD_115200
604#define CONSOLE_BAUD_RATE 115200
605#endif
606
607 p0.h = hi(UART_GCTL);
608 p0.l = lo(UART_GCTL);
609 r0 = 0x00(Z);
610 w[p0] = r0.L; /* To Turn off UART clocks */
611 ssync;
612
613 p0.h = hi(UART_LCR);
614 p0.l = lo(UART_LCR);
615 r0 = 0x83(Z);
616 w[p0] = r0.L; /* To enable DLL writes */
617 ssync;
618
619 R1 = (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_SCLK_DIV) / (CONSOLE_BAUD_RATE * 16));
620
621 p0.h = hi(UART_DLL);
622 p0.l = lo(UART_DLL);
623 r0 = 0xFF(Z);
624 r0 = R1 & R0;
625 w[p0] = r0.L;
626 ssync;
627
628 p0.h = hi(UART_DLH);
629 p0.l = lo(UART_DLH);
630 r1 >>= 8 ;
631 w[p0] = r1.L;
632 ssync;
633
634 p0.h = hi(UART_GCTL);
635 p0.l = lo(UART_GCTL);
636 r0 = 0x0(Z);
637 w[p0] = r0.L; /* To enable UART clock */
638 ssync;
639
640 p0.h = hi(UART_LCR);
641 p0.l = lo(UART_LCR);
642 r0 = 0x03(Z);
643 w[p0] = r0.L; /* To Turn on UART */
644 ssync;
645
646 p0.h = hi(UART_GCTL);
647 p0.l = lo(UART_GCTL);
648 r0 = 0x01(Z);
649 w[p0] = r0.L; /* To Turn on UART Clocks */
650 ssync;
651
652 P0.h = hi(UART_THR);
653 P0.l = lo(UART_THR);
654 P1.h = hi(UART_LSR);
655 P1.l = lo(UART_LSR);
656
657 R0.L = 'K';
658 call .Lwait_char;
659 R0.L='e';
660 call .Lwait_char;
661 R0.L='r';
662 call .Lwait_char;
663 R0.L='n'
664 call .Lwait_char;
665 R0.L='e'
666 call .Lwait_char;
667 R0.L='l';
668 call .Lwait_char;
669 R0.L=' ';
670 call .Lwait_char;
671 R0.L='c';
672 call .Lwait_char;
673 R0.L='r';
674 call .Lwait_char;
675 R0.L='a';
676 call .Lwait_char;
677 R0.L='s';
678 call .Lwait_char;
679 R0.L='h';
680 call .Lwait_char;
681 R0.L='\r';
682 call .Lwait_char;
683 R0.L='\n';
684 call .Lwait_char;
685
686 R0.L='S';
687 call .Lwait_char;
688 R0.L='E';
689 call .Lwait_char;
690 R0.L='Q'
691 call .Lwait_char;
692 R0.L='S'
693 call .Lwait_char;
694 R0.L='T';
695 call .Lwait_char;
696 R0.L='A';
697 call .Lwait_char;
698 R0.L='T';
699 call .Lwait_char;
700 R0.L='=';
701 call .Lwait_char;
702 R2 = SEQSTAT;
703 call .Ldump_reg;
704
705 R0.L=' ';
706 call .Lwait_char;
707 R0.L='R';
708 call .Lwait_char;
709 R0.L='E'
710 call .Lwait_char;
711 R0.L='T'
712 call .Lwait_char;
713 R0.L='X';
714 call .Lwait_char;
715 R0.L='=';
716 call .Lwait_char;
717 R2 = RETX;
718 call .Ldump_reg;
719
720 R0.L='\r';
721 call .Lwait_char;
722 R0.L='\n';
723 call .Lwait_char;
724
725.Ldebug_kernel_start_trap_done:
726 JUMP .Ldebug_kernel_start_trap_done;
727.Ldump_reg:
728 R3 = 32;
729 R4 = 0x0F;
730 R5 = ':'; /* one past 9 */
731
732.Ldump_reg2:
733 R0 = R2;
734 R3 += -4;
735 R0 >>>= R3;
736 R0 = R0 & R4;
737 R0 += 0x30;
738 CC = R0 <= R5;
739 if CC JUMP .Ldump_reg1;
740 R0 += 7;
741
742.Ldump_reg1:
743 R1.l = W[P1];
744 CC = BITTST(R1, 5);
745 if !CC JUMP .Ldump_reg1;
746 W[P0] = r0;
747
748 CC = R3 == 0;
749 if !CC JUMP .Ldump_reg2
750 RTS;
751
752.Lwait_char:
753 R1.l = W[P1];
754 CC = BITTST(R1, 5);
755 if !CC JUMP .Lwait_char;
756 W[P0] = r0;
757 RTS;
758
759#endif /* CONFIG_DEBUG_KERNEL_START */
760
761.data
762
763/*
764 * Set up the usable of RAM stuff. Size of RAM is determined then
765 * an initial stack set up at the end.
766 */
767
768.align 4
769__rambase:
770.long 0
771__ramstart:
772.long 0
773__ramend:
774.long 0
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 01:05:49 -0500